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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-16 11:50:59 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-16 11:50:59 +0200 |
| commit | fb72fae0a907684c00bb19950ad9a20c21732f77 (patch) | |
| tree | 66408fda742506d59f443b369ecf4b46ffe9605a /src/synth | |
| parent | 9810f6ae993e18e6a711ee0289498d1c105d889d (diff) | |
| download | ghdl-fb72fae0a907684c00bb19950ad9a20c21732f77.tar.gz ghdl-fb72fae0a907684c00bb19950ad9a20c21732f77.tar.bz2 ghdl-fb72fae0a907684c00bb19950ad9a20c21732f77.zip | |
vhdl: declare verification units (WIP).
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synthesis.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb index 7ebb9602e..a84b4976a 100644 --- a/src/synth/synthesis.adb +++ b/src/synth/synthesis.adb @@ -102,6 +102,8 @@ package body Synthesis is null; when Iir_Kind_Architecture_Body => null; + when Iir_Kinds_Verification_Unit => + null; end case; end if; Next (Dep_It); |