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| author | Tristan Gingold <tgingold@free.fr> | 2016-10-15 14:32:32 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-10-15 14:32:32 +0200 |
| commit | 6c9ac1f1ba0492c2d5add773d2024dd163b31db4 (patch) | |
| tree | 9ccb3faa5b7f43f98acf342f6bbadcef3017c062 /src/vhdl/simulate/annotations.adb | |
| parent | 0d82b72ca11cb249888356caec800ddd43a70c82 (diff) | |
| download | ghdl-6c9ac1f1ba0492c2d5add773d2024dd163b31db4.tar.gz ghdl-6c9ac1f1ba0492c2d5add773d2024dd163b31db4.tar.bz2 ghdl-6c9ac1f1ba0492c2d5add773d2024dd163b31db4.zip | |
simulation: remove sim_be after previous code factorization.
Diffstat (limited to 'src/vhdl/simulate/annotations.adb')
| -rw-r--r-- | src/vhdl/simulate/annotations.adb | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/src/vhdl/simulate/annotations.adb b/src/vhdl/simulate/annotations.adb index 4758b5bed..c4c6fded1 100644 --- a/src/vhdl/simulate/annotations.adb +++ b/src/vhdl/simulate/annotations.adb @@ -595,11 +595,20 @@ package body Annotations is procedure Annotate_Declaration (Block_Info: Sim_Info_Acc; Decl: Iir) is begin case Get_Kind (Decl) is - when Iir_Kind_Delayed_Attribute - | Iir_Kind_Stable_Attribute - | Iir_Kind_Quiet_Attribute - | Iir_Kind_Transaction_Attribute - | Iir_Kind_Signal_Declaration => + when Iir_Kind_Signal_Attribute_Declaration => + declare + Attr : Iir; + begin + Attr := Get_Signal_Attribute_Chain (Decl); + while Is_Valid (Attr) loop + Annotate_Anonymous_Type_Definition + (Block_Info, Get_Type (Attr)); + Create_Signal_Info (Block_Info, Attr); + Attr := Get_Attr_Chain (Attr); + end loop; + end; + + when Iir_Kind_Signal_Declaration => Annotate_Anonymous_Type_Definition (Block_Info, Get_Type (Decl)); Create_Signal_Info (Block_Info, Decl); |