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author | Tristan Gingold <tgingold@free.fr> | 2016-02-20 06:48:03 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2016-02-20 06:51:08 +0100 |
commit | 002d948aeead104b745e3175e1c684ec7b928847 (patch) | |
tree | 1b04a8d48bdbc164f4e0998f9eb4e1cc0bfe0930 /src/vhdl/simulate/elaboration.adb | |
parent | 49328d94b6bfce72ecc76dc1c9d5c612ebdd2d6c (diff) | |
download | ghdl-002d948aeead104b745e3175e1c684ec7b928847.tar.gz ghdl-002d948aeead104b745e3175e1c684ec7b928847.tar.bz2 ghdl-002d948aeead104b745e3175e1c684ec7b928847.zip |
Refactoring in simulate in order to link with ortho.
Diffstat (limited to 'src/vhdl/simulate/elaboration.adb')
-rw-r--r-- | src/vhdl/simulate/elaboration.adb | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb index 46eecb5ee..14a915ec2 100644 --- a/src/vhdl/simulate/elaboration.adb +++ b/src/vhdl/simulate/elaboration.adb @@ -21,14 +21,14 @@ with Str_Table; with Errorout; use Errorout; with Evaluation; with Execution; use Execution; -with Simulation; use Simulation; +--with Simulation; use Simulation; with Iirs_Utils; use Iirs_Utils; with Libraries; with Name_Table; with File_Operation; with Iir_Chains; use Iir_Chains; with Grt.Types; use Grt.Types; -with Simulation.AMS; use Simulation.AMS; +with Elaboration.AMS; use Elaboration.AMS; with Areapools; use Areapools; with Grt.Errors; with Grt.Options; @@ -2817,6 +2817,8 @@ package body Elaboration is -- Use a 'fake' process to execute code during elaboration. Current_Process := No_Process; + Instance_Pool := Global_Pool'Access; + pragma Assert (Is_Empty (Expr_Pool)); -- Find architecture and configuration for the top unit @@ -2866,6 +2868,8 @@ package body Elaboration is Current_Process := null; + Instance_Pool := null; + -- Stop now in case of errors. if Nbr_Errors /= 0 then Grt.Errors.Fatal_Error; |