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authorTristan Gingold <tgingold@free.fr>2019-05-09 18:20:41 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-09 18:20:41 +0200
commitb9c2c358ac74c66736537d5b1eb44d42819f6ec1 (patch)
treef04c0faad2b7d566bac6783e7166a060ede6a693 /src/vhdl/simulate/simul-elaboration-ams.ads
parentf526c1f41a2f5a8a5f70ee33f82d9e6b84117142 (diff)
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Make lists a generic package, add vhdl-lists.
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