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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-08 06:49:26 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-08 06:49:26 +0200 |
| commit | 2a21ee61dd73224bec023b3a541c9d4ddaee0f88 (patch) | |
| tree | 7c52809e7d50133ae408621761b1d2b8a9254de1 /src/vhdl/simulate/simul-elaboration.adb | |
| parent | 7c464546f0c202bfa95b6516a19effea16f30289 (diff) | |
| download | ghdl-2a21ee61dd73224bec023b3a541c9d4ddaee0f88.tar.gz ghdl-2a21ee61dd73224bec023b3a541c9d4ddaee0f88.tar.bz2 ghdl-2a21ee61dd73224bec023b3a541c9d4ddaee0f88.zip | |
synth: handle integer +/- for constants.
Diffstat (limited to 'src/vhdl/simulate/simul-elaboration.adb')
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index f21c623eb..1638aa721 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1903,7 +1903,8 @@ package body Simul.Elaboration is Elaborate_Psl_Directive (Instance, Stmt); when Iir_Kind_Concurrent_Simple_Signal_Assignment - | Iir_Kind_Concurrent_Selected_Signal_Assignment => + | Iir_Kind_Concurrent_Selected_Signal_Assignment + | Iir_Kind_Concurrent_Conditional_Signal_Assignment => -- In case concurrent signal assignemnts were not -- canonicalized. null; |