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| author | Tristan Gingold <tgingold@free.fr> | 2017-12-23 18:19:43 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-01-02 12:11:19 +0100 |
| commit | de4766d9b15d458e7ef963a5157536b0f459dbe9 (patch) | |
| tree | 8ba3c2e6e6bd021d4763ec8421c054f5c11c0ddd /src/vhdl/simulate/simul-elaboration.adb | |
| parent | d9e4e63079c7c4b5b965414a53679d502fe4a233 (diff) | |
| download | ghdl-de4766d9b15d458e7ef963a5157536b0f459dbe9.tar.gz ghdl-de4766d9b15d458e7ef963a5157536b0f459dbe9.tar.bz2 ghdl-de4766d9b15d458e7ef963a5157536b0f459dbe9.zip | |
simul: remove ports_map from instances (not used).
Diffstat (limited to 'src/vhdl/simulate/simul-elaboration.adb')
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index 2163c80ff..73a31b287 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -354,7 +354,6 @@ package body Simul.Elaboration is Parent => Father, Children => null, Brother => null, - Ports_Map => Null_Iir, Marker => Empty_Marker, Objects => (others => null), Elab_Objects => 0, @@ -1290,9 +1289,6 @@ package body Simul.Elaboration is Actual : Iir; Formal : Iir; begin - pragma Assert (Formal_Instance.Ports_Map = Null_Iir); - Formal_Instance.Ports_Map := Map; - if Ports = Null_Iir then return; end if; @@ -3009,7 +3005,6 @@ package body Simul.Elaboration is Parent => null, Children => null, Brother => null, - Ports_Map => Null_Iir, Marker => Empty_Marker, Actuals_Ref => null, Result => null, |