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author | Tristan Gingold <tgingold@free.fr> | 2019-05-05 07:18:49 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-05 08:05:10 +0200 |
commit | 53fcf00d88d1a3b34c7833aa4c421ea52f3e03dd (patch) | |
tree | 1d54f41e948b16a5ff6ad0cedafccf978a13bd89 /src/vhdl/simulate/simul-execution.adb | |
parent | d1f0fedf7882cf1b15ea6450da5bbd878d007a98 (diff) | |
download | ghdl-53fcf00d88d1a3b34c7833aa4c421ea52f3e03dd.tar.gz ghdl-53fcf00d88d1a3b34c7833aa4c421ea52f3e03dd.tar.bz2 ghdl-53fcf00d88d1a3b34c7833aa4c421ea52f3e03dd.zip |
vhdl: move sem* packages to vhdl children.
Diffstat (limited to 'src/vhdl/simulate/simul-execution.adb')
-rw-r--r-- | src/vhdl/simulate/simul-execution.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb index f034bb9b6..3a1c11028 100644 --- a/src/vhdl/simulate/simul-execution.adb +++ b/src/vhdl/simulate/simul-execution.adb @@ -44,7 +44,7 @@ with Grt.Errors; with Grt.Std_Logic_1164; with Grt.Lib; with Grt.Strings; -with Sem_Inst; +with Vhdl.Sem_Inst; package body Simul.Execution is @@ -3344,7 +3344,7 @@ package body Simul.Execution is if Res /= Null_Iir then return Res; else - Orig := Sem_Inst.Get_Origin (Spec); + Orig := Vhdl.Sem_Inst.Get_Origin (Spec); pragma Assert (Orig /= Null_Iir); return Get_Subprogram_Body_Origin (Orig); end if; @@ -3361,7 +3361,7 @@ package body Simul.Execution is if Res /= Null_Iir then return Res; else - Orig := Sem_Inst.Get_Origin (Spec); + Orig := Vhdl.Sem_Inst.Get_Origin (Spec); return Get_Protected_Type_Body_Origin (Orig); end if; end Get_Protected_Type_Body_Origin; |