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| author | Tristan Gingold <tgingold@free.fr> | 2016-11-02 06:25:11 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-12-12 04:16:56 +0100 |
| commit | 0897f0c90d65995da152e1a15ad7a1bca6651cc7 (patch) | |
| tree | 51432ed2ef0dddf9e1ff4052d850f36669d81376 /src/vhdl/simulate/simulation-main.adb | |
| parent | 5ccabe2c5f9d88b8f3065cafc8c156b35f5fb502 (diff) | |
| download | ghdl-0897f0c90d65995da152e1a15ad7a1bca6651cc7.tar.gz ghdl-0897f0c90d65995da152e1a15ad7a1bca6651cc7.tar.bz2 ghdl-0897f0c90d65995da152e1a15ad7a1bca6651cc7.zip | |
ownership: fix ghdlsimul
Diffstat (limited to 'src/vhdl/simulate/simulation-main.adb')
| -rw-r--r-- | src/vhdl/simulate/simulation-main.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simulation-main.adb b/src/vhdl/simulate/simulation-main.adb index 0faf6254c..1b7f1eb63 100644 --- a/src/vhdl/simulate/simulation-main.adb +++ b/src/vhdl/simulate/simulation-main.adb @@ -676,11 +676,11 @@ package body Simulation.Main is Formal_Expr : Iir_Value_Literal_Acc; Local_Instance : Block_Instance_Acc; Local_Expr : Iir_Value_Literal_Acc; + Inter : Iir; Assoc : Iir_Association_Element_By_Expression) is pragma Unreferenced (Formal_Instance); Formal : constant Iir := Get_Formal (Assoc); - Inter : constant Iir := Get_Association_Interface (Assoc); begin if False and Trace_Elaboration then Put ("connect formal "); @@ -767,7 +767,7 @@ package body Simulation.Main is begin Set_Connect (E.Formal_Instance, E.Formal, E.Actual_Instance, E.Actual, - E.Assoc); + E.Inter, E.Assoc); end; end loop; |