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| author | Tristan Gingold <tgingold@free.fr> | 2016-02-15 19:56:28 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-02-17 21:04:45 +0100 |
| commit | 10fb178950f03784ef9316bfc70570b644cc2855 (patch) | |
| tree | 0f5cd7b160ccce746a4a871f6a6b340ff303cba3 /src/vhdl/simulate/simulation.adb | |
| parent | 228c201e45fd56cb3a32fed0abb6285a95fa9c91 (diff) | |
| download | ghdl-10fb178950f03784ef9316bfc70570b644cc2855.tar.gz ghdl-10fb178950f03784ef9316bfc70570b644cc2855.tar.bz2 ghdl-10fb178950f03784ef9316bfc70570b644cc2855.zip | |
simul debugger: add info instances
Diffstat (limited to 'src/vhdl/simulate/simulation.adb')
| -rw-r--r-- | src/vhdl/simulate/simulation.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb index 728e7b0cb..a3d58bcd7 100644 --- a/src/vhdl/simulate/simulation.adb +++ b/src/vhdl/simulate/simulation.adb @@ -1834,8 +1834,8 @@ package body Simulation is end loop; if In_Signals /= 0 then - Error_Msg_Elab ("top entity should not have inputs signals", Entity); - -- raise Simulation_Error; + Warning_Msg_Elab + ("top entity should not have inputs signals", Entity); end if; if Disp_Stats then |