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| author | Tristan Gingold <tgingold@free.fr> | 2018-11-15 18:34:35 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-11-15 18:34:35 +0100 |
| commit | 44e1952ebdf419bea19e287ba895f34941747a54 (patch) | |
| tree | 5756687298e1e9d873eea60d43b82e46aad3aaf9 /src/vhdl/simulate | |
| parent | e0f94103e7b528beb652ace2d602632afc76d812 (diff) | |
| download | ghdl-44e1952ebdf419bea19e287ba895f34941747a54.tar.gz ghdl-44e1952ebdf419bea19e287ba895f34941747a54.tar.bz2 ghdl-44e1952ebdf419bea19e287ba895f34941747a54.zip | |
simul: adjust after previous changes.
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index 1e71d7c4f..bb8bc79f1 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -26,6 +26,7 @@ with Libraries; with Name_Table; with Simul.File_Operation; with Iir_Chains; use Iir_Chains; +with Sem_Lib; use Sem_Lib; with Simul.Annotations; use Simul.Annotations; with Simul.Elaboration.AMS; use Simul.Elaboration.AMS; with Areapools; use Areapools; @@ -528,7 +529,7 @@ package body Simul.Elaboration is (Get_Need_Body (Library_Unit) or else Get_Date (Body_Design) /= Date_Obsolete) then - Libraries.Load_Design_Unit (Body_Design, Design_Unit); + Load_Design_Unit (Body_Design, Design_Unit); else Body_Design := Null_Iir; end if; @@ -2087,7 +2088,7 @@ package body Simul.Elaboration is end if; Arch_Name := Get_Identifier (Arch); end if; - Arch_Design := Libraries.Load_Secondary_Unit + Arch_Design := Load_Secondary_Unit (Get_Design_Unit (Entity), Arch_Name, Stmt); if Arch_Design = Null_Iir then Error_Msg_Elab |