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| author | Tristan Gingold <tgingold@free.fr> | 2019-05-23 18:34:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-05-23 18:34:47 +0200 |
| commit | 7506f3876dd547edc1d3e954bc862a25c76a8968 (patch) | |
| tree | 68239c2ae5bcbdb7a59635113c35b8bc015a1390 /src/vhdl/simulate | |
| parent | 7cdf0ab35669516ea520b0d5ac783384f641e551 (diff) | |
| download | ghdl-7506f3876dd547edc1d3e954bc862a25c76a8968.tar.gz ghdl-7506f3876dd547edc1d3e954bc862a25c76a8968.tar.bz2 ghdl-7506f3876dd547edc1d3e954bc862a25c76a8968.zip | |
vhdl/simulate: ignore some constructs for synthesis.
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/simul-annotations.adb | 5 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 3 |
2 files changed, 5 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index 2cbbfe181..8fb4c4fdc 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -1020,9 +1020,10 @@ package body Simul.Annotations is when Iir_Kind_Simple_Simultaneous_Statement => null; - when Iir_Kind_Concurrent_Simple_Signal_Assignment => + when Iir_Kind_Concurrent_Simple_Signal_Assignment + | Iir_Kind_Concurrent_Selected_Signal_Assignment => -- In case concurrent signal assignemnts were not - -- canonicalized. + -- canonicalized (for synthesis). null; when others => diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index e1a418d6e..f21c623eb 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1902,7 +1902,8 @@ package body Simul.Elaboration is | Iir_Kind_Psl_Endpoint_Declaration => Elaborate_Psl_Directive (Instance, Stmt); - when Iir_Kind_Concurrent_Simple_Signal_Assignment => + when Iir_Kind_Concurrent_Simple_Signal_Assignment + | Iir_Kind_Concurrent_Selected_Signal_Assignment => -- In case concurrent signal assignemnts were not -- canonicalized. null; |