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| author | Tristan Gingold <tgingold@free.fr> | 2016-07-04 04:01:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-07-05 08:06:42 +0200 |
| commit | a4cfa53675aac53107a8eac45b41e159e6add805 (patch) | |
| tree | ba49b0ae453e7f4bb5680342d87431e53b5d982a /src/vhdl/simulate | |
| parent | cedac9ece9eb113691d614d480256de7b7b65332 (diff) | |
| download | ghdl-a4cfa53675aac53107a8eac45b41e159e6add805.tar.gz ghdl-a4cfa53675aac53107a8eac45b41e159e6add805.tar.bz2 ghdl-a4cfa53675aac53107a8eac45b41e159e6add805.zip | |
Fix indentation and English mistakes.
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/sim_be.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/simulate/sim_be.adb b/src/vhdl/simulate/sim_be.adb index 49a146879..59eacc814 100644 --- a/src/vhdl/simulate/sim_be.adb +++ b/src/vhdl/simulate/sim_be.adb @@ -30,12 +30,12 @@ package body Sim_Be is procedure Finish_Compilation (Unit: Iir_Design_Unit; Main: Boolean := False) is use Ada.Text_IO; - Lib_Unit : Iir; + Lib_Unit : constant Iir := Get_Library_Unit (Unit); begin - Lib_Unit := Get_Library_Unit (Unit); -- Semantic analysis. + if Flags.Verbose then - Put_Line ("semantize " & Disp_Node (Lib_Unit)); + Put_Line ("analyze " & Disp_Node (Lib_Unit)); end if; Sem.Semantic (Unit); |