psl: cover directive works on a sequence, not on a property.

2 files changed, 48 insertions, 2 deletions

diff --git a/src/vhdl/simulate/debugger.adb b/src/vhdl/simulate/debugger.adb
index bbb16e231..47846394a 100644
--- a/src/vhdl/simulate/debugger.adb
+++ b/src/vhdl/simulate/debugger.adb
@@ -1298,6 +1298,42 @@ package body Debugger is
       return Walk_Continue;
    end Cb_Disp_File;
 
+   procedure Info_PSL_Proc (Line : String)
+   is
+      pragma Unreferenced (Line);
+   begin
+      if PSL_Table.Last < PSL_Table.First then
+         Put_Line ("no PSL directive");
+         return;
+      end if;
+
+      for I in PSL_Table.First .. PSL_Table.Last loop
+         declare
+            E : PSL_Entry renames PSL_Table.Table (I);
+         begin
+            Disp_Instance_Name (E.Instance);
+            Put ('.');
+            Put (Name_Table.Image (Get_Identifier (E.Stmt)));
+            New_Line;
+            Disp_Vhdl.Disp_PSL_NFA (Get_PSL_NFA (E.Stmt));
+            Put ("    01234567890123456789012345678901234567890123456789");
+            for I in E.States'Range loop
+               if I mod 50 = 0 then
+                  New_Line;
+                  Put (Int32'Image (I / 10));
+                  Put (": ");
+               end if;
+               if E.States (I) then
+                  Put ('*');
+               else
+                  Put ('.');
+               end if;
+            end loop;
+            New_Line;
+         end;
+      end loop;
+   end Info_PSL_Proc;
+
    procedure Info_Stats_Proc (Line : String) is
       P : Natural := Line'First;
       E : Natural;
@@ -1324,7 +1360,8 @@ package body Debugger is
       end if;
    end Info_Stats_Proc;
 
-   procedure Info_Files_Proc (Line : String) is
+   procedure Info_Files_Proc (Line : String)
+   is
       pragma Unreferenced (Line);
       Status : Walk_Status;
    begin
@@ -1706,10 +1743,16 @@ package body Debugger is
       end loop;
    end Cont_Proc;
 
+   Menu_Info_Psl : aliased Menu_Entry :=
+     (Kind => Menu_Command,
+      Name => new String'("psl"),
+      Next => null,
+      Proc => Info_PSL_Proc'Access);
+
    Menu_Info_Stats : aliased Menu_Entry :=
      (Kind => Menu_Command,
       Name => new String'("stats"),
-      Next => null,
+      Next => Menu_Info_Psl'Access,
       Proc => Info_Stats_Proc'Access);
 
    Menu_Info_Tree : aliased Menu_Entry :=
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb
index b02d47dd2..c33997b7d 100644
--- a/src/vhdl/simulate/simulation.adb
+++ b/src/vhdl/simulate/simulation.adb
@@ -1112,6 +1112,9 @@ package body Simulation is
       Release (Marker, Expr_Pool);
       if V then
          Nvec := (others => False);
+         if Get_Kind (E.Stmt) = Iir_Kind_Psl_Cover_Statement then
+            Nvec (0) := True;
+         end if;
 
          --  For each state: if set, evaluate all outgoing edges.
          NFA := Get_PSL_NFA (E.Stmt);