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authorTristan Gingold <tgingold@free.fr>2019-05-10 21:43:00 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-10 21:43:00 +0200
commitb76ff335a807be97a79e272b5e9bf08a99d3d8d6 (patch)
tree414e004aaaa69fa5a7987028ba54429e0707e3a3 /src/vhdl/simulate
parent4be73be561379cff6b0e5966e020d90387085034 (diff)
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vhdl: decouple errorouts a bit more.
Diffstat (limited to 'src/vhdl/simulate')
-rw-r--r--src/vhdl/simulate/simul-elaboration.adb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index 996a36804..05ea592e2 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -396,7 +396,7 @@ package body Simul.Elaboration is
Create_Instance_Value (Instance);
if Trace_Elaboration then
- Report_Msg (Msgid_Note, Errorout.Elaboration, No_Location,
+ Report_Msg (Msgid_Note, Errorout.Elaboration, No_Source_Coord,
"elaborating %n", (1 => +Decl));
end if;
@@ -447,7 +447,7 @@ package body Simul.Elaboration is
Block.Objects (Package_Info.Pkg_Slot).Instance;
begin
if Trace_Elaboration then
- Report_Msg (Msgid_Note, Errorout.Elaboration, No_Location,
+ Report_Msg (Msgid_Note, Errorout.Elaboration, No_Source_Coord,
"elaborating %n", (1 => +Decl));
end if;