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| author | Tristan Gingold <tgingold@free.fr> | 2019-05-07 07:49:52 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-05-07 07:49:52 +0200 |
| commit | cc951b301b52286677f36c390e077e9d3a3ea793 (patch) | |
| tree | 9282f8939305ed249ad528d533cda0657495411f /src/vhdl/simulate | |
| parent | 492288d13db59eb946ef44dc4c5b4fa815217791 (diff) | |
| download | ghdl-cc951b301b52286677f36c390e077e9d3a3ea793.tar.gz ghdl-cc951b301b52286677f36c390e077e9d3a3ea793.tar.bz2 ghdl-cc951b301b52286677f36c390e077e9d3a3ea793.zip | |
vhdl-nodes_utils: renaming.
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index 862d5d34c..0d006f3a5 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1572,7 +1572,7 @@ package body Simul.Elaboration is Local := Get_Chain (Local); end loop; - Sub_Chain_Init (First, Last); + Chain_Init (First, Last); Formal := Formal_Chain; for I in Assoc_List'Range loop if Assoc_List (I) = Null_Iir then @@ -1587,7 +1587,7 @@ package body Simul.Elaboration is end if; Set_Whole_Association_Flag (Assoc, True); Set_Formal (Assoc, Formal); - Sub_Chain_Append (First, Last, Assoc); + Chain_Append (First, Last, Assoc); Formal := Get_Chain (Formal); end loop; |