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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-11 21:09:39 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-13 06:30:27 +0100 |
| commit | d70084ccb149ff4f5fca072c672b1f3d040358a9 (patch) | |
| tree | 1b2cb2172368b02be2f5c92bab1f59583ec4dec9 /src/vhdl/simulate | |
| parent | 5c398db1b18a346cf2cb25acac07b068ccd7deee (diff) | |
| download | ghdl-d70084ccb149ff4f5fca072c672b1f3d040358a9.tar.gz ghdl-d70084ccb149ff4f5fca072c672b1f3d040358a9.tar.bz2 ghdl-d70084ccb149ff4f5fca072c672b1f3d040358a9.zip | |
psl: keep denoting names in the PSL ast.
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index ae768b3d0..fcac44e3d 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -374,7 +374,8 @@ package body Simul.Simulation.Main is use PSL.Nodes; begin case Get_Kind (Expr) is - when N_HDL_Expr => + when N_HDL_Expr + | N_HDL_Bool => declare E : constant Iir := Get_HDL_Node (Expr); Rtype : constant Iir := Get_Base_Type (Get_Type (E)); |