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authorTristan Gingold <tgingold@free.fr>2019-05-05 07:18:49 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-05 08:05:10 +0200
commit53fcf00d88d1a3b34c7833aa4c421ea52f3e03dd (patch)
tree1d54f41e948b16a5ff6ad0cedafccf978a13bd89 /src/vhdl/translate/ortho_front.adb
parentd1f0fedf7882cf1b15ea6450da5bbd878d007a98 (diff)
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vhdl: move sem* packages to vhdl children.
Diffstat (limited to 'src/vhdl/translate/ortho_front.adb')
-rw-r--r--src/vhdl/translate/ortho_front.adb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/translate/ortho_front.adb b/src/vhdl/translate/ortho_front.adb
index 208348ef4..3fc6f4e81 100644
--- a/src/vhdl/translate/ortho_front.adb
+++ b/src/vhdl/translate/ortho_front.adb
@@ -29,8 +29,8 @@ with Std_Package;
with Flags;
with Configuration;
with Translation;
-with Sem;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
with Errorout; use Errorout;
with Errorout.Console;
with GNAT.OS_Lib;
@@ -317,7 +317,7 @@ package body Ortho_Front is
-- Do late analysis checks.
Design := Get_First_Design_Unit (New_Design_File);
while Is_Valid (Design) loop
- Sem.Sem_Analysis_Checks_List
+ Vhdl.Sem.Sem_Analysis_Checks_List
(Design, Is_Warning_Enabled (Warnid_Delayed_Checks));
Design := Get_Chain (Design);
end loop;