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authorTristan Gingold <tgingold@free.fr>2019-05-05 07:18:49 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-05 08:05:10 +0200
commit53fcf00d88d1a3b34c7833aa4c421ea52f3e03dd (patch)
tree1d54f41e948b16a5ff6ad0cedafccf978a13bd89 /src/vhdl/translate/trans-chap2.adb
parentd1f0fedf7882cf1b15ea6450da5bbd878d007a98 (diff)
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vhdl: move sem* packages to vhdl children.
Diffstat (limited to 'src/vhdl/translate/trans-chap2.adb')
-rw-r--r--src/vhdl/translate/trans-chap2.adb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb
index 01703b842..433d18443 100644
--- a/src/vhdl/translate/trans-chap2.adb
+++ b/src/vhdl/translate/trans-chap2.adb
@@ -19,7 +19,7 @@
with Std_Names;
with Std_Package; use Std_Package;
with Errorout; use Errorout;
-with Sem_Inst;
+with Vhdl.Sem_Inst;
with Nodes_Meta;
with Iirs_Utils; use Iirs_Utils;
with Trans.Chap3;
@@ -1377,7 +1377,7 @@ package body Trans.Chap2 is
Kind : constant Iir_Kind := Get_Kind (N);
Fields : constant Fields_Array := Get_Fields (Kind);
F : Fields_Enum;
- Orig : constant Iir := Sem_Inst.Get_Origin (N);
+ Orig : constant Iir := Vhdl.Sem_Inst.Get_Origin (N);
pragma Assert (Orig /= Null_Iir);
Orig_Info : constant Ortho_Info_Acc := Get_Info (Orig);
Info : Ortho_Info_Acc;
@@ -1489,7 +1489,7 @@ package body Trans.Chap2 is
begin
Inter := Chain;
while Inter /= Null_Iir loop
- Orig := Sem_Inst.Get_Origin (Inter);
+ Orig := Vhdl.Sem_Inst.Get_Origin (Inter);
Orig_Info := Get_Info (Orig);
Info := Add_Info (Inter, Orig_Info.Kind);