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| author | Tristan Gingold <tgingold@free.fr> | 2021-04-05 08:56:13 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-04-05 08:56:13 +0200 |
| commit | a9f68a1d91f8ea2a74d8ad4c34f9c777746848a4 (patch) | |
| tree | 8994a975e6ddd5c9ec7aea2e6ceaab2c44629e10 /src/vhdl/vhdl-nodes.ads | |
| parent | b0e6f54aba3912da5ad84e90ebc53b08ba716733 (diff) | |
| download | ghdl-a9f68a1d91f8ea2a74d8ad4c34f9c777746848a4.tar.gz ghdl-a9f68a1d91f8ea2a74d8ad4c34f9c777746848a4.tar.bz2 ghdl-a9f68a1d91f8ea2a74d8ad4c34f9c777746848a4.zip | |
vhdl: add Iir_Kind_Foreign_Module
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index d86ebdf86..7d79ca43d 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -203,6 +203,7 @@ package Vhdl.Nodes is -- -- Get/Set_Last_Design_Unit (Field6) -- + -- Source file entry for this file. -- Get/Set_Design_File_Source (Field7) -- -- Identifier for the design file file name and dirname. @@ -266,6 +267,25 @@ package Vhdl.Nodes is -- Get/Set_Configuration_Mark_Flag (Flag4) -- Get/Set_Configuration_Done_Flag (Flag5) + -- Iir_Kind_Foreign_Module (Medium) + -- + -- Get/Set_Design_File (Field0) + -- Get/Set_Parent (Alias Field0) + -- + -- Get/Set_Identifier (Field3) + -- + -- Get/Set_Foreign_Node (Field1) + -- + -- Get/Set_Date (Field4) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Hash_Chain (Field7) + -- + -- Get/Set_Date_State (State1) + -- + -- Get/Set_Elab_Flag (Flag3) + -- Iir_Kind_Library_Clause (Short) -- -- LRM08 13.2 Design libraries @@ -4821,7 +4841,10 @@ package Vhdl.Nodes is Iir_Kind_Error, Iir_Kind_Design_File, + Iir_Kind_Design_Unit, + Iir_Kind_Foreign_Module, + Iir_Kind_Library_Clause, Iir_Kind_Use_Clause, Iir_Kind_Context_Reference, @@ -6351,6 +6374,10 @@ package Vhdl.Nodes is --Iir_Kind_Package_Body Iir_Kind_Architecture_Body; + subtype Iir_Kinds_Design_Unit is Iir_Kind range + Iir_Kind_Design_Unit .. + Iir_Kind_Foreign_Module; + subtype Iir_Kinds_Primary_Unit is Iir_Kind range Iir_Kind_Entity_Declaration .. --Iir_Kind_Configuration_Declaration @@ -9252,4 +9279,8 @@ package Vhdl.Nodes is -- Field: Field3 Ref function Get_Default_Clock (N : Iir) return Iir; procedure Set_Default_Clock (N : Iir; Clk : Iir); + + -- Field: Field1 (uc) + function Get_Foreign_Node (N : Iir) return Int32; + procedure Set_Foreign_Node (N : Iir; En : Int32); end Vhdl.Nodes; |