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authorTristan Gingold <tgingold@free.fr>2022-07-21 06:45:24 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-21 06:45:24 +0200
commit341a8698ccb6b795d46b9570bac06e240c7664de (patch)
treef818881d50e3da9fe055cbf3a6ce4c2472e16aaf /src/vhdl/vhdl-sem.adb
parentf440e1b0289a1f969b9190a11831e384b911db0e (diff)
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vhdl-nodes: renaming.
Node Iir_Kind_Signal_Attribute_Declaration is now Iir_Kind_Attribute_Implicit_Declaration Will also handle quantities.
Diffstat (limited to 'src/vhdl/vhdl-sem.adb')
-rw-r--r--src/vhdl/vhdl-sem.adb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb
index 20b5f13ad..8510398ff 100644
--- a/src/vhdl/vhdl-sem.adb
+++ b/src/vhdl/vhdl-sem.adb
@@ -2887,7 +2887,7 @@ package body Vhdl.Sem is
is
Unit : constant Iir_Design_Unit := Get_Design_Unit (Pkg);
Header : constant Iir := Get_Package_Header (Pkg);
- Implicit : Implicit_Signal_Declaration_Type;
+ Implicit : Implicit_Declaration_Type;
begin
Sem_Scopes.Add_Name (Pkg);
Set_Visible_Flag (Pkg, True);
@@ -3462,7 +3462,7 @@ package body Vhdl.Sem is
Library : constant Iir := Get_Library (Get_Design_File (Design_Unit));
Prev_Unit : Iir;
Old_Design_Unit : Iir_Design_Unit;
- Implicit : Implicit_Signal_Declaration_Type;
+ Implicit : Implicit_Declaration_Type;
begin
-- Sanity check: can analyze either previously analyzed unit or just
-- parsed unit.