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authorPepijn de Vos <pepijndevos@gmail.com>2019-08-20 19:11:10 +0200
committertgingold <tgingold@users.noreply.github.com>2019-08-20 19:11:10 +0200
commit27ddfe66da98ad3ea058d29730454b19045d8621 (patch)
treedf59c777410e1bcb87c1790cb19bc883c7e590a4 /src/vhdl
parentf64f2dbaa0e613f3ee499e6d474074d1b21c8bf4 (diff)
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initial support for reduce and/or (#900)
Diffstat (limited to 'src/vhdl')
-rw-r--r--src/vhdl/vhdl-ieee-std_logic_1164.adb23
-rw-r--r--src/vhdl/vhdl-nodes.ads4
2 files changed, 22 insertions, 5 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 58ce60769..14468e1c4 100644
--- a/src/vhdl/vhdl-ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -277,11 +277,24 @@ package body Vhdl.Ieee.Std_Logic_1164 is
end case;
Set_Implicit_Definition (Decl, Predefined);
end;
- elsif Is_Vector_Function (Decl)
- and then Get_Identifier (Decl) = Name_Not
- then
- Set_Implicit_Definition
- (Decl, Iir_Predefined_Ieee_1164_Vector_Not);
+ elsif Is_Vector_Function (Decl) then
+ declare
+ Predefined : Iir_Predefined_Functions;
+ begin
+ case Get_Identifier (Decl) is
+ when Name_Not =>
+ Predefined := Iir_Predefined_Ieee_1164_Vector_Not;
+ when Name_And =>
+ Predefined :=
+ Iir_Predefined_Ieee_1164_Vector_And_Reduce;
+ when Name_Or =>
+ Predefined :=
+ Iir_Predefined_Ieee_1164_Vector_Or_Reduce;
+ when others =>
+ Predefined := Iir_Predefined_None;
+ end case;
+ Set_Implicit_Definition (Decl, Predefined);
+ end;
end if;
end if;
end loop;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index ac3f5979a..41ef5fd9e 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4901,6 +4901,10 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_1164_Vector_Xnor,
Iir_Predefined_Ieee_1164_Vector_Not,
+ -- VHDL-2008 unary logic operators
+ Iir_Predefined_Ieee_1164_Vector_And_Reduce,
+ Iir_Predefined_Ieee_1164_Vector_Or_Reduce,
+
-- Numeric_Std.
-- Abbreviations:
-- Uns: Unsigned, Sgn: Signed, Nat: Natural, Int: Integer.