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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-29 06:55:52 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-29 06:55:52 +0200 |
| commit | 698c668481e9ca77234317bca7047efd8210c24c (patch) | |
| tree | 2853048fbd75630e90eb2f350ee19aa0517060ba /src/vhdl | |
| parent | c794aaa2a7dbec514d188c28f75da181a5692992 (diff) | |
| download | ghdl-698c668481e9ca77234317bca7047efd8210c24c.tar.gz ghdl-698c668481e9ca77234317bca7047efd8210c24c.tar.bz2 ghdl-698c668481e9ca77234317bca7047efd8210c24c.zip | |
synth: add support for record types.
(WIP: need to fix regression of stmt01).
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-annotations.adb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index 1e3b00043..d81e70adf 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -410,6 +410,10 @@ package body Vhdl.Annotations is end if; when Iir_Kind_Record_Type_Definition => + if Flag_Synthesis then + -- For the offsets. + Create_Object_Info (Block_Info, Def, Kind_Type); + end if; declare List : constant Iir_Flist := Get_Elements_Declaration_List (Def); |