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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-02 19:48:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-02 20:24:52 +0200 |
| commit | c3b78f3370c1def22ff7240045d174fb120714e9 (patch) | |
| tree | 5a23d1658b640d9eb3980d7c64a46e8124707c93 /src/vhdl | |
| parent | 749a21ac4d7a55be99f4f91ec31ff762586589b3 (diff) | |
| download | ghdl-c3b78f3370c1def22ff7240045d174fb120714e9.tar.gz ghdl-c3b78f3370c1def22ff7240045d174fb120714e9.tar.bz2 ghdl-c3b78f3370c1def22ff7240045d174fb120714e9.zip | |
grt: slightly simplify the interface.
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index fcac44e3d..956d0f3dc 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -1212,7 +1212,7 @@ package body Simul.Simulation.Main is procedure Simulation_Entity (Top_Conf : Iir_Design_Unit) is use Grt.Errors; - Stop : Boolean; + Ok : C_Boolean; Status : Integer; begin Break_Time := Std_Time'Last; @@ -1225,8 +1225,8 @@ package body Simul.Simulation.Main is Debug (Reason_Start); end if; - Grt.Main.Run_Elab (Stop); - if Stop then + Ok := Grt.Main.Run_Elab; + if not Ok then return; end if; |