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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-13 04:39:50 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-14 07:44:19 +0200 |
| commit | 020e7d55e49116f5bed02a7913823cd09770a1f2 (patch) | |
| tree | 84010b67d586ef71ec04f15de6020ac419adb7d3 /src | |
| parent | 270d9354950e917b34c15661aedbc1ef58261b56 (diff) | |
| download | ghdl-020e7d55e49116f5bed02a7913823cd09770a1f2.tar.gz ghdl-020e7d55e49116f5bed02a7913823cd09770a1f2.tar.bz2 ghdl-020e7d55e49116f5bed02a7913823cd09770a1f2.zip | |
synth-vhdl_stmts: handle attribute names in expressions
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index f2abd6df7..ad7382da9 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -108,7 +108,8 @@ package body Synth.Vhdl_Stmts is Dest_Dyn : out Dyn_Name) is begin case Get_Kind (Pfx) is - when Iir_Kind_Simple_Name => + when Iir_Kind_Simple_Name + | Iir_Kind_Attribute_Name => Synth_Assignment_Prefix (Syn_Inst, Get_Named_Entity (Pfx), Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); when Iir_Kind_Interface_Signal_Declaration @@ -121,6 +122,7 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Interface_File_Declaration | Iir_Kind_Non_Object_Alias_Declaration | Iir_Kind_Object_Alias_Declaration + | Iir_Kind_Attribute_Value | Iir_Kind_Free_Quantity_Declaration | Iir_Kinds_Branch_Quantity_Declaration | Iir_Kind_Dot_Attribute => |