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authorTristan Gingold <tgingold@free.fr>2020-03-26 12:57:55 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-26 12:57:55 +0100
commit0d36b145f729e5a72822e8f881cb23620a8ffe52 (patch)
treee533f5469828fd7e6f6716d01a7bbfa0e2c0c70c /src
parent60d7fa83b5e3a0da1ba4d5a7900a83bd1548b1ce (diff)
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netlists-gates: improve comments.
Diffstat (limited to 'src')
-rw-r--r--src/synth/netlists-gates.ads5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index 7ea18d4a0..6435b24e9 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -225,10 +225,13 @@ package Netlists.Gates is
subtype Dyn_Insert_Module_Id is
Module_Id range Id_Dyn_Insert .. Id_Dyn_Insert_En;
+ -- Input0: index
+ -- Param0: step
+ -- Param1: max
-- OUT := IN0 * STEP, IN0 < MAX
Id_Memidx : constant Module_Id := 72;
- -- OUT := IN0 + IN1, size extension.
+ -- OUT := IN0 + IN1, size extension (max of inputs width).
Id_Addidx : constant Module_Id := 73;
-- Represent a memory with a fixed size.