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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-28 07:42:55 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-28 07:42:55 +0200 |
| commit | 1048f7b66fc74c09e7fc2afc2df1bac6516c9912 (patch) | |
| tree | 628dbb7bd0b6b1fdaa5d84efabf7316a15767f15 /src | |
| parent | 9652c2bdfe75e90784910a0dd7d0f03dd97e0067 (diff) | |
| download | ghdl-1048f7b66fc74c09e7fc2afc2df1bac6516c9912.tar.gz ghdl-1048f7b66fc74c09e7fc2afc2df1bac6516c9912.tar.bz2 ghdl-1048f7b66fc74c09e7fc2afc2df1bac6516c9912.zip | |
synth: disp_vhdl: handle mux2
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 31 | ||||
| -rw-r--r-- | src/synth/netlists-gates.ads | 4 |
2 files changed, 32 insertions, 3 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 37e3acdaf..c9e779925 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -35,13 +35,18 @@ package body Netlists.Disp_Vhdl is end if; end Put_Trim; + procedure Put_Uns32 (V : Uns32) is + begin + Put_Trim (Uns32'Image (V)); + end Put_Uns32; + procedure Put_Type (W : Width) is begin if W = 1 then Put ("std_logic"); else Put ("std_logic_vector ("); - Put_Trim (Width'Image (W - 1)); + Put_Uns32 (W - 1); Put (" downto 0)"); end if; end Put_Type; @@ -53,7 +58,7 @@ package body Netlists.Disp_Vhdl is procedure Put_Name_Version (N : Sname) is begin - Put_Trim (Uns32'Image (Get_Sname_Version (N))); + Put_Uns32 (Get_Sname_Version (N)); end Put_Name_Version; procedure Put_Name_1 (N : Sname) @@ -236,7 +241,7 @@ package body Netlists.Disp_Vhdl is P_Idx := Get_Param_Idx (P); Put_Interface_Name (Get_Param_Desc (Imod, P_Idx).Name); Put (" => "); - Put_Trim (Uns32'Image (Get_Param_Uns32 (Inst, P_Idx))); + Put_Uns32 (Get_Param_Uns32 (Inst, P_Idx)); end loop; Put_Line (")"); Put_Line (" port map ("); @@ -317,6 +322,20 @@ package body Netlists.Disp_Vhdl is Put (" <= not "); Disp_Net_Name (Get_Input_Net (Inst, 0)); Put_Line (";"); + when Id_Extract => + declare + O : constant Net := Get_Output (Inst, 0); + Wd : constant Width := Get_Width (O); + Off : constant Uns32 := Get_Param_Uns32 (Inst, 0); + begin + Disp_Template (" \1 <= \2 (", (O, Get_Input_Net (Inst, 0))); + if Wd > 1 then + Put_Uns32 (Off + Wd - 1); + Put (" downto "); + end if; + Put_Uns32 (Off); + Put_Line (");"); + end; when Id_Const_UB32 => declare O : constant Net := Get_Output (Inst, 0); @@ -372,6 +391,12 @@ package body Netlists.Disp_Vhdl is " end if;" & NL & " end process;" & NL, (1 => Clk, 2 => D, 3 => O)); end; + when Id_Mux2 => + Disp_Template (" \4 <= \2 when \1 = '0' else \3;" & NL, + (1 => Get_Input_Net (Inst, 0), + 2 => Get_Input_Net (Inst, 1), + 3 => Get_Input_Net (Inst, 2), + 4 => Get_Output (Inst, 0))); when others => Disp_Instance_Gate (Inst); end case; diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index c4d96df47..90615dc7a 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -65,7 +65,11 @@ package Netlists.Gates is Id_Split2 : constant Module_Id := 25; Id_Split3 : constant Module_Id := 26; + -- Inputs: s, i0, i1 + -- Output: o Id_Mux2 : constant Module_Id := 27; + -- Inputs: s, i0, i1, s2, s3 + -- Output: o Id_Mux4 : constant Module_Id := 28; -- Like a wire: the output is equal to the input, but could be elimited |