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| author | Tristan Gingold <tgingold@free.fr> | 2019-06-30 13:45:32 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-06-30 13:45:32 +0200 |
| commit | 10b2f5a4012ae368dfcf49628281e34674f913d7 (patch) | |
| tree | 3f388e873f00f3196f7a8aadc62eb4d45616974a /src | |
| parent | fd8bd4eb19cae6b17ada917f428d52030651f752 (diff) | |
| download | ghdl-10b2f5a4012ae368dfcf49628281e34674f913d7.tar.gz ghdl-10b2f5a4012ae368dfcf49628281e34674f913d7.tar.bz2 ghdl-10b2f5a4012ae368dfcf49628281e34674f913d7.zip | |
synth: handle 2 states fsms.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-stmts.adb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 2f2b85fe6..7ac5053e2 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -526,7 +526,11 @@ package body Synth.Stmts is -- If the width is not a multiple of 2, handle the last level. if Wd mod 2 = 1 then - Sub_Sel := Build_Extract_Bit (Build_Context, Sel, Wd - 1); + if Wd = 1 then + Sub_Sel := Sel; + else + Sub_Sel := Build_Extract_Bit (Build_Context, Sel, Wd - 1); + end if; Iels := Els'First; Oels := Els'First; while Iels <= Lels loop |