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authorTristan Gingold <tgingold@free.fr>2021-04-16 06:44:30 +0200
committerTristan Gingold <tgingold@free.fr>2021-04-16 06:58:03 +0200
commit17fe76dff5ac755c6d3162bdd21c49508ada566e (patch)
treea467bb14eca0b4df3a6ac45a8c76a5e3dee09137 /src
parent33b307ba8d64ae952334a7f79249178141adee2c (diff)
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synth: renaming (synth.oper -> synth.vhdl_oper)
Diffstat (limited to 'src')
-rw-r--r--src/synth/synth-expr.adb2
-rw-r--r--src/synth/synth-static_oper.adb8
-rw-r--r--src/synth/synth-vhdl_oper.adb (renamed from src/synth/synth-oper.adb)8
-rw-r--r--src/synth/synth-vhdl_oper.ads (renamed from src/synth/synth-oper.ads)4
4 files changed, 11 insertions, 11 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 437318257..6c50ab6a9 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -43,7 +43,7 @@ with Synth.Errors; use Synth.Errors;
with Synth.Environment;
with Synth.Decls;
with Synth.Stmts; use Synth.Stmts;
-with Synth.Oper; use Synth.Oper;
+with Synth.Vhdl_Oper; use Synth.Vhdl_Oper;
with Synth.Heap; use Synth.Heap;
with Synth.Debugger;
with Synth.Vhdl_Aggr;
diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb
index bd53f73b9..dca886777 100644
--- a/src/synth/synth-static_oper.adb
+++ b/src/synth/synth-static_oper.adb
@@ -29,7 +29,7 @@ with Netlists; use Netlists;
with Synth.Errors; use Synth.Errors;
with Synth.Source; use Synth.Source;
with Synth.Expr; use Synth.Expr;
-with Synth.Oper;
+with Synth.Vhdl_Oper;
with Synth.Ieee.Std_Logic_1164; use Synth.Ieee.Std_Logic_1164;
with Synth.Ieee.Numeric_Std; use Synth.Ieee.Numeric_Std;
with Synth.Files_Operations;
@@ -299,7 +299,7 @@ package body Synth.Static_Oper is
Res_St : Type_Acc;
Res : Memtyp;
begin
- Bnd := Oper.Create_Bounds_From_Length
+ Bnd := Synth.Vhdl_Oper.Create_Bounds_From_Length
(Syn_Inst, Get_Index_Type (Get_Type (Expr), 0),
L_Len + R_Len);
Res_St := Create_Onedimensional_Array_Subtype (Res_Typ, Bnd);
@@ -320,7 +320,7 @@ package body Synth.Static_Oper is
Res_St : Type_Acc;
Res : Memtyp;
begin
- Bnd := Oper.Create_Bounds_From_Length
+ Bnd := Synth.Vhdl_Oper.Create_Bounds_From_Length
(Syn_Inst, Get_Index_Type (Get_Type (Expr), 0), 1 + Rlen);
Res_St := Create_Onedimensional_Array_Subtype (Res_Typ, Bnd);
Res := Create_Memory (Res_St);
@@ -336,7 +336,7 @@ package body Synth.Static_Oper is
Res_St : Type_Acc;
Res : Memtyp;
begin
- Bnd := Oper.Create_Bounds_From_Length
+ Bnd := Synth.Vhdl_Oper.Create_Bounds_From_Length
(Syn_Inst, Get_Index_Type (Get_Type (Expr), 0), Llen + 1);
Res_St := Create_Onedimensional_Array_Subtype (Res_Typ, Bnd);
Res := Create_Memory (Res_St);
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-vhdl_oper.adb
index 99c3c474b..9aaf725d1 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-vhdl_oper.adb
@@ -38,9 +38,9 @@ with Synth.Expr; use Synth.Expr;
with Synth.Source;
with Synth.Static_Oper; use Synth.Static_Oper;
-package body Synth.Oper is
+package body Synth.Vhdl_Oper is
procedure Set_Location (N : Net; Loc : Node)
- renames Synth.Source.Set_Location;
+ renames Standard.Synth.Source.Set_Location;
function Synth_Uresize
(Ctxt : Context_Acc; Val : Valtyp; W : Width; Loc : Node) return Net
@@ -1784,7 +1784,7 @@ package body Synth.Oper is
-- which must represent all positive values in the bounds using a
-- signed word (so that -1 is also represented).
Max := Int32'Max (Left.Typ.Vbound.Left, Left.Typ.Vbound.Right);
- W := Utils.Clog2 (Uns32 (Max)) + 1;
+ W := Netlists.Utils.Clog2 (Uns32 (Max)) + 1;
Rng := (Dir => Dir_To,
Is_Signed => True,
Left => -1,
@@ -2148,4 +2148,4 @@ package body Synth.Oper is
return Synth_Dyadic_Operation (Syn_Inst, Imp, Op1, Op2, Expr);
end if;
end Synth_Operator_Function_Call;
-end Synth.Oper;
+end Synth.Vhdl_Oper;
diff --git a/src/synth/synth-oper.ads b/src/synth/synth-vhdl_oper.ads
index c3d84dec6..7efa711d9 100644
--- a/src/synth/synth-oper.ads
+++ b/src/synth/synth-vhdl_oper.ads
@@ -22,7 +22,7 @@ with Synth.Objtypes; use Synth.Objtypes;
with Synth.Values; use Synth.Values;
with Synth.Vhdl_Context; use Synth.Vhdl_Context;
-package Synth.Oper is
+package Synth.Vhdl_Oper is
function Synth_Predefined_Function_Call
(Syn_Inst : Synth_Instance_Acc; Expr : Node) return Valtyp;
function Synth_Operator_Function_Call
@@ -43,4 +43,4 @@ package Synth.Oper is
(Syn_Inst : Synth_Instance_Acc; Atype : Iir; Len : Iir_Index32)
return Bound_Type;
-end Synth.Oper;
+end Synth.Vhdl_Oper;