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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-11 20:20:30 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-11 20:29:22 +0100 |
| commit | 1c18a124dc6749ef95c89012bf45ea1f2cdfa0d7 (patch) | |
| tree | 640c31af501a5c8c5ce0d7ad0b54ce5ee29dbcd3 /src | |
| parent | a9d4cba091789f10eb25ccbcbc4d832c8847cf67 (diff) | |
| download | ghdl-1c18a124dc6749ef95c89012bf45ea1f2cdfa0d7.tar.gz ghdl-1c18a124dc6749ef95c89012bf45ea1f2cdfa0d7.tar.bz2 ghdl-1c18a124dc6749ef95c89012bf45ea1f2cdfa0d7.zip | |
netlists-gates: add comments.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-gates.ads | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index f5b7e0492..b2a40fbf1 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -126,8 +126,11 @@ package Netlists.Gates is -- A simple DFF with an initial value (must be constant). This is -- for FPGAs. + -- Input 0: Clock + -- Input 1: Data Id_Idff : constant Module_Id := 52; -- A DFF with an asynchronous reset and an initial value. + -- Input 2: Initial value. Id_Iadff : constant Module_Id := 53; -- Width change: truncate or extend. Sign is know in order to possibly |