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| author | Tristan Gingold <tgingold@free.fr> | 2022-12-22 08:08:35 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-12-22 08:08:35 +0100 |
| commit | 236f7eddef51acba2718eeda8431a1a68c7e231e (patch) | |
| tree | 7c81b3fb8346e51bd0d95a548ea4dc1b12ecf3c6 /src | |
| parent | 2e6cf50ff058c46b545385be33f331430f75f5d9 (diff) | |
| download | ghdl-236f7eddef51acba2718eeda8431a1a68c7e231e.tar.gz ghdl-236f7eddef51acba2718eeda8431a1a68c7e231e.tar.bz2 ghdl-236f7eddef51acba2718eeda8431a1a68c7e231e.zip | |
synth: handle element in target aggregate. Fix #2279
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index adab6e89a..58e04afad 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -331,9 +331,13 @@ package body Synth.Vhdl_Stmts is while Choice /= Null_Node loop pragma Assert (Get_Kind (Choice) = Iir_Kind_Choice_By_None); El := Get_Associated_Expr (Choice); - El_Typ := Elab.Vhdl_Expr.Exec_Name_Subtype (Syn_Inst, El); - Bnd := Get_Array_Bound (El_Typ); - Len := Len + Bnd.Len; + if Get_Element_Type_Flag (Choice) then + Len := Len + 1; + else + El_Typ := Elab.Vhdl_Expr.Exec_Name_Subtype (Syn_Inst, El); + Bnd := Get_Array_Bound (El_Typ); + Len := Len + Bnd.Len; + end if; Choice := Get_Chain (Choice); end loop; end; |