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| author | Tristan Gingold <tgingold@free.fr> | 2022-02-05 17:04:58 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-02-05 17:06:03 +0100 |
| commit | 265881a175f2e9a9f222b0d06780811c6ab6cd93 (patch) | |
| tree | 91d6bc3dad6955fa9653bce24021a825b8f57052 /src | |
| parent | 74c6885ae93ddaf061c7728382e2db75328a3023 (diff) | |
| download | ghdl-265881a175f2e9a9f222b0d06780811c6ab6cd93.tar.gz ghdl-265881a175f2e9a9f222b0d06780811c6ab6cd93.tar.bz2 ghdl-265881a175f2e9a9f222b0d06780811c6ab6cd93.zip | |
synth-vhdl_aggr: fix mismatch. Fix #1962
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_aggr.adb | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb index 6ba9fda0d..6e7d3447f 100644 --- a/src/synth/synth-vhdl_aggr.adb +++ b/src/synth/synth-vhdl_aggr.adb @@ -486,7 +486,10 @@ package body Synth.Vhdl_Aggr is begin Els_Typ := Create_Rec_El_Array (Aggr_Type.Rec.Len); for I in Els_Typ.E'Range loop - Els_Typ.E (I).Typ := Tab_Res (Nat32 (I)).Typ; + -- Note: elements are put in reverse order in Tab_Res, + -- so reverse again... + Els_Typ.E (I).Typ := + Tab_Res (Tab_Res'Last - Nat32 (I) + 1).Typ; end loop; Res_Typ := Create_Record_Type (Els_Typ); end; @@ -497,6 +500,8 @@ package body Synth.Vhdl_Aggr is if Const_P then Res := Create_Value_Memory (Res_Typ); for I in Aggr_Type.Rec.E'Range loop + -- Note: elements are put in reverse order in Tab_Res, + -- so reverse again... Write_Value (Res.Val.Mem + Res_Typ.Rec.E (I).Moff, Tab_Res (Tab_Res'Last - Nat32 (I) + 1)); end loop; |