diff options
| author | Tristan Gingold <tgingold@free.fr> | 2018-02-03 20:20:42 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-02-06 06:23:28 +0100 |
| commit | 2b340dbb3738bb694e427e8b73aff1fdef636f4d (patch) | |
| tree | 6d49214ed2fc3ae73c4545f3198992e3f26cdd31 /src | |
| parent | 8c9447bad365140e56415e1cc510964ef77b52a8 (diff) | |
| download | ghdl-2b340dbb3738bb694e427e8b73aff1fdef636f4d.tar.gz ghdl-2b340dbb3738bb694e427e8b73aff1fdef636f4d.tar.bz2 ghdl-2b340dbb3738bb694e427e8b73aff1fdef636f4d.zip | |
std_names: add localparam, trior, triand..
Diffstat (limited to 'src')
| -rw-r--r-- | src/std_names.adb | 4 | ||||
| -rw-r--r-- | src/std_names.ads | 21 |
2 files changed, 18 insertions, 7 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index b14c3fc4b..f7a589210 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -491,6 +491,8 @@ package body Std_Names is Def ("tri", Name_Tri); Def ("tri0", Name_Tri0); Def ("tri1", Name_Tri1); + Def ("triand", Name_Triand); + Def ("trior", Name_Trior); Def ("trireg", Name_Trireg); Def ("wand", Name_Wand); Def ("weak0", Name_Weak0); @@ -498,6 +500,8 @@ package body Std_Names is Def ("wire", Name_Wire); Def ("wor", Name_Wor); + Def ("localparam", Name_Localparam); + Def ("define", Name_Define); Def ("endif", Name_Endif); Def ("ifdef", Name_Ifdef); diff --git a/src/std_names.ads b/src/std_names.ads index 4b2da18e9..b078f4b72 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -568,16 +568,23 @@ package Std_Names is Name_Tri : constant Name_Id := Name_First_Verilog + 61; Name_Tri0 : constant Name_Id := Name_First_Verilog + 62; Name_Tri1 : constant Name_Id := Name_First_Verilog + 63; - Name_Trireg : constant Name_Id := Name_First_Verilog + 64; - Name_Wand : constant Name_Id := Name_First_Verilog + 65; - Name_Weak0 : constant Name_Id := Name_First_Verilog + 66; - Name_Weak1 : constant Name_Id := Name_First_Verilog + 67; - Name_Wire : constant Name_Id := Name_First_Verilog + 68; - Name_Wor : constant Name_Id := Name_First_Verilog + 69; + Name_Triand : constant Name_Id := Name_First_Verilog + 64; + Name_Trior : constant Name_Id := Name_First_Verilog + 65; + Name_Trireg : constant Name_Id := Name_First_Verilog + 66; + Name_Wand : constant Name_Id := Name_First_Verilog + 67; + Name_Weak0 : constant Name_Id := Name_First_Verilog + 68; + Name_Weak1 : constant Name_Id := Name_First_Verilog + 69; + Name_Wire : constant Name_Id := Name_First_Verilog + 70; + Name_Wor : constant Name_Id := Name_First_Verilog + 71; Name_Last_Verilog : constant Name_Id := Name_Wor; + -- Verilog 2001 + Name_First_V2001 : constant Name_Id := Name_Last_Verilog + 1; + Name_Localparam : constant Name_Id := Name_First_V2001; + Name_Last_V2001 : constant Name_Id := Name_First_V2001 + 0; + -- Verilog Directives. - Name_First_Directive : constant Name_Id := Name_Last_Verilog + 1; + Name_First_Directive : constant Name_Id := Name_Last_V2001 + 1; Name_Define : constant Name_Id := Name_First_Directive + 00; Name_Endif : constant Name_Id := Name_First_Directive + 01; Name_Ifdef : constant Name_Id := Name_First_Directive + 02; |