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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-08 18:38:35 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-08 18:38:35 +0200 |
| commit | 32272b4c7e384e0f54a8216ee14db5b8554f9793 (patch) | |
| tree | 41938d8538566cfa48fc3221f429a733de8869b0 /src | |
| parent | 55e0a382c3fa5a9873249b18a75cd340cf1366f2 (diff) | |
| download | ghdl-32272b4c7e384e0f54a8216ee14db5b8554f9793.tar.gz ghdl-32272b4c7e384e0f54a8216ee14db5b8554f9793.tar.bz2 ghdl-32272b4c7e384e0f54a8216ee14db5b8554f9793.zip | |
synth-disp_vhdl: handle array/record of 1 element.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index d2e83fb6d..abff34d9e 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -203,6 +203,8 @@ package body Synth.Disp_Vhdl is Disp_Pfx (Off, W, Full); end Disp_Out_Rhs; + -- PTYPE is the type of the original port, while TYP is the type of + -- the netlist port. procedure Disp_Out_Converter (Mname : String; Pfx : String; Off : Uns32; @@ -261,7 +263,11 @@ package body Synth.Disp_Vhdl is if Btype = Vhdl.Ieee.Std_Logic_1164.Std_Logic_Vector_Type then -- Nothing to do. W := Typ.Vbound.Len; - Put (" " & Pfx & " <= "); + Put (" " & Pfx); + if W = 1 then + Put (" (" & Pfx & "'left)"); + end if; + Put (" <= "); Disp_Out_Rhs (Mname, Off, W, Full); Put_Line (";"); elsif Btype = Vhdl.Std_Package.Bit_Vector_Type_Definition then @@ -314,6 +320,7 @@ package body Synth.Disp_Vhdl is declare Els : constant Node_Flist := Get_Elements_Declaration_List (Ptype); + Rec_Full : constant Boolean := Full and Typ.W = 1; begin for I in Flist_First .. Flist_Last (Els) loop declare @@ -324,7 +331,7 @@ package body Synth.Disp_Vhdl is Disp_Out_Converter (Mname, Pfx & '.' & Name_Table.Image (Get_Identifier (El)), - Off + Et.Off, Get_Type (El), Et.Typ, False); + Off + Et.Off, Get_Type (El), Et.Typ, Rec_Full); end; end loop; end; @@ -333,8 +340,9 @@ package body Synth.Disp_Vhdl is end case; end Disp_Out_Converter; + -- Disp conversion for output port (so in the form o <= wrap_o). procedure Disp_Output_Port_Converter (Inst : Synth_Instance_Acc; - Port : Node) + Port : Node) is Port_Name : constant String := Name_Table.Image (Get_Identifier (Port)); |