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| author | Tristan Gingold <tgingold@free.fr> | 2017-12-05 05:19:27 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-12-05 05:19:27 +0100 |
| commit | 344ca60dd3b9cc8547951a5573b1bb209b3e7b5b (patch) | |
| tree | f06e09e77138bbc5f900de9c26583594ddf0f821 /src | |
| parent | 237ff6b3749f8e8bcab5040fcb04feeec77da92b (diff) | |
| download | ghdl-344ca60dd3b9cc8547951a5573b1bb209b3e7b5b.tar.gz ghdl-344ca60dd3b9cc8547951a5573b1bb209b3e7b5b.tar.bz2 ghdl-344ca60dd3b9cc8547951a5573b1bb209b3e7b5b.zip | |
simul: psl default clock, unaffected waveform.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/simulate/simul-annotations.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-execution.adb | 2 |
3 files changed, 8 insertions, 0 deletions
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index fb03495e4..4c6e6e80b 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -717,6 +717,9 @@ package body Simul.Annotations is when Iir_Kind_Nature_Declaration => null; + when Iir_Kind_Psl_Default_Clock => + null; + when others => Error_Kind ("annotate_declaration", Decl); end case; diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index 7cfb0c352..55e40bfa9 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -2684,6 +2684,9 @@ package body Simul.Elaboration is when Iir_Kinds_Branch_Quantity_Declaration => Elaborate_Branch_Quantity_Declaration (Instance, Decl); + when Iir_Kind_Psl_Default_Clock => + null; + when others => Error_Kind ("elaborate_declaration", Decl); end case; diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb index ae3818792..bdcb42ebc 100644 --- a/src/vhdl/simulate/simul-execution.adb +++ b/src/vhdl/simulate/simul-execution.adb @@ -4021,6 +4021,8 @@ package body Simul.Execution is Disconnect_Signal (Rdest); Release (Marker, Expr_Pool); return; + elsif Get_Kind (Wf) = Iir_Kind_Unaffected_Waveform then + return; end if; Transactions.Stmt := Stmt; |