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authorOndrej Ille <ondrej.ille@gmail.com>2021-04-10 08:55:11 +0200
committertgingold <tgingold@users.noreply.github.com>2021-04-11 08:41:10 +0200
commit4db4532626c97a24037dd855e8044ad0639e3a71 (patch)
treea23c79ae0aa4483dbe0e27258b70fc828af3acff /src
parent686d61a8a1bfb16cb1b1eda52ec07dde23efd995 (diff)
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src: Allow case generate only in VHDL 2008.
Diffstat (limited to 'src')
-rw-r--r--src/vhdl/vhdl-parse.adb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb
index 696dc43a2..d3cc8e0b2 100644
--- a/src/vhdl/vhdl-parse.adb
+++ b/src/vhdl/vhdl-parse.adb
@@ -10201,6 +10201,7 @@ package body Vhdl.Parse is
Stmt := Parse_If_Generate_Statement (Label, Loc);
when Tok_Case =>
Postponed_Not_Allowed;
+ Check_Vhdl_At_Least_2008 ("case generate");
Stmt := Parse_Case_Generate_Statement (Label, Loc);
when Tok_Component
| Tok_Entity