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| author | Tristan Gingold <tgingold@free.fr> | 2020-01-01 21:14:20 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-01-01 21:14:20 +0100 |
| commit | 4defa9eaf8694042abc1fb87dc957c7b6a0e56f9 (patch) | |
| tree | b6979a5992cbc3416bfc99ea33096707a0d7e53b /src | |
| parent | 467a0f2ae8ba8762ffbdd53bbdaf786c02c4ff2c (diff) | |
| download | ghdl-4defa9eaf8694042abc1fb87dc957c7b6a0e56f9.tar.gz ghdl-4defa9eaf8694042abc1fb87dc957c7b6a0e56f9.tar.bz2 ghdl-4defa9eaf8694042abc1fb87dc957c7b6a0e56f9.zip | |
synth-disp_vhdl: handle conversion from signed integers.
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-disp_vhdl.adb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/synth/synth-disp_vhdl.adb b/src/synth/synth-disp_vhdl.adb index e2687d04d..43392147c 100644 --- a/src/synth/synth-disp_vhdl.adb +++ b/src/synth/synth-disp_vhdl.adb @@ -125,7 +125,11 @@ package body Synth.Disp_Vhdl is if W > 1 then Put ("std_logic_vector("); end if; - Put ("to_unsigned("); + if Typ.Drange.Is_Signed then + Put ("to_signed("); + else + Put ("to_unsigned("); + end if; Put (Pfx & "," & Width'Image (W) & ")"); if W > 1 then Put (")"); |