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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-12 05:21:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-12 05:21:42 +0200 |
| commit | 551a1519162dbc68fd03f8d435381b0693e1aaa1 (patch) | |
| tree | f0acf50ec0e6590bd7ff62c1324fc36b5093edfb /src | |
| parent | b1c8c9a1e6a32ed390a2e73c928ca15762ec20b2 (diff) | |
| download | ghdl-551a1519162dbc68fd03f8d435381b0693e1aaa1.tar.gz ghdl-551a1519162dbc68fd03f8d435381b0693e1aaa1.tar.bz2 ghdl-551a1519162dbc68fd03f8d435381b0693e1aaa1.zip | |
simul: factorize code for conversion functions
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 25 |
1 files changed, 6 insertions, 19 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 646496a66..744df677d 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -1811,30 +1811,16 @@ package body Simul.Vhdl_Simul is Mode : Resolver_Read_Mode; Index : Ghdl_Index_Type) is + S : constant Ghdl_Signal_Ptr := Read_Sig (Sig); Val : Ghdl_Value_Ptr; begin - case Dst.Typ.Kind is - when Type_Bit - | Type_Logic - | Type_Discrete => - null; - when others => - raise Internal_Error; - end case; case Mode is when Read_Port => - Val := Ghdl_Signal_Read_Port (Read_Sig (Sig), Index); + Val := Ghdl_Signal_Read_Port (S, Index); when Read_Driver => - Val := Ghdl_Signal_Read_Driver (Read_Sig (Sig), Index); - end case; - case Dst.Typ.Kind is - when Type_Bit => - Write_U8 (Dst.Mem, Ghdl_B1'Pos (Val.B1)); - when Type_Logic => - Write_U8 (Dst.Mem, Val.E8); - when others => - raise Internal_Error; + Val := Ghdl_Signal_Read_Driver (S, Index); end case; + Write_Ghdl_Value (Dst, Val.all); end Resolver_Read_Value; type Read_Signal_Enum is @@ -1895,7 +1881,8 @@ package body Simul.Vhdl_Simul is begin case Val.Typ.Kind is when Type_Bit - | Type_Logic => + | Type_Logic + | Type_Discrete => S := Read_Sig (Sig); case Attr is when Write_Signal_Driving_Value => |