synth-vhdl_eval: handle to_X01 for bit to std_ulogic.

Fix #2307

3 files changed, 39 insertions, 0 deletions

diff --git a/src/synth/synth-ieee-std_logic_1164.ads b/src/synth/synth-ieee-std_logic_1164.ads
index 20ebe4be1..a81947c54 100644
--- a/src/synth/synth-ieee-std_logic_1164.ads
+++ b/src/synth/synth-ieee-std_logic_1164.ads
@@ -55,6 +55,9 @@ package Synth.Ieee.Std_Logic_1164 is
 
    function To_Bit (S : Std_Ulogic; Xmap : Bit) return Bit;
 
+   type Table_Bit_Log_Type is array (Bit) of Std_Ulogic;
+   Bit2log_Table : Table_Bit_Log_Type := ('0', '1');
+
    type Table_1d is array (Std_Ulogic) of Std_Ulogic;
    type Table_2d is array (Std_Ulogic, Std_Ulogic) of Std_Ulogic;
 
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb
index 126c8a735..d9b1bc2a8 100644
--- a/src/synth/synth-vhdl_eval.adb
+++ b/src/synth/synth-vhdl_eval.adb
@@ -2756,6 +2756,15 @@ package body Synth.Vhdl_Eval is
                B := Map_X01Z (B);
                return Create_Memory_U8 (Std_Ulogic'Pos (B), Res_Typ);
             end;
+         when Iir_Predefined_Ieee_1164_To_X01_Bit_Log =>
+            declare
+               B : Bit;
+               S : Std_Ulogic;
+            begin
+               B := Read_Bit (Param1.Mem, 0);
+               S := Bit2log_Table (B);
+               return Create_Memory_U8 (Std_Ulogic'Pos (S), Res_Typ);
+            end;
          when Iir_Predefined_Ieee_1164_To_X01_Slv
             | Iir_Predefined_Ieee_Numeric_Std_To_X01_Uns
             | Iir_Predefined_Ieee_Numeric_Std_To_X01_Sgn =>
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 207d2f0c5..93c8dec8e 100644
--- a/src/vhdl/vhdl-ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -41,6 +41,13 @@ package body Vhdl.Ieee.Std_Logic_1164 is
       return Base_Type = Std_Package.Bit_Vector_Type_Definition;
    end Is_Bitvec_Parameter;
 
+   function Is_Bit_Parameter (Inter : Iir) return Boolean
+   is
+      Base_Type : constant Iir := Get_Base_Type (Get_Type (Inter));
+   begin
+      return Base_Type = Std_Package.Bit_Type_Definition;
+   end Is_Bit_Parameter;
+
    function Is_Integer_Parameter (Inter : Iir) return Boolean is
    begin
       return (Get_Base_Type (Get_Type (Inter))
@@ -219,6 +226,24 @@ package body Vhdl.Ieee.Std_Logic_1164 is
       return True;
    end Is_Bitvec_Function;
 
+   --  Return True iff the profile of FUNC is: (l : bit)
+   function Is_Bit_Function (Func : Iir) return Boolean
+   is
+      Inter : constant Iir := Get_Interface_Declaration_Chain (Func);
+   begin
+      if Get_Implicit_Definition (Func) /= Iir_Predefined_None then
+         return False;
+      end if;
+      if Inter = Null_Iir or else not Is_Bit_Parameter (Inter) then
+         return False;
+      end if;
+      if Get_Chain (Inter) /= Null_Iir then
+         return False;
+      end if;
+
+      return True;
+   end Is_Bit_Function;
+
    procedure Extract_Declarations (Pkg : Iir_Package_Declaration)
    is
       Error : exception;
@@ -382,6 +407,8 @@ package body Vhdl.Ieee.Std_Logic_1164 is
                      Predefined := Iir_Predefined_Ieee_1164_To_X01_Slv;
                   elsif Is_Scalar_Function (Decl) then
                      Predefined := Iir_Predefined_Ieee_1164_To_X01_Log;
+                  elsif Is_Bit_Function (Decl) then
+                     Predefined := Iir_Predefined_Ieee_1164_To_X01_Bit_Log;
                   end if;
                when Name_To_UX01 =>
                   if Is_Vector_Function (Decl) then