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author | Tristan Gingold <tgingold@free.fr> | 2019-09-20 04:50:31 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-20 04:50:31 +0200 |
commit | 6448431a20876b11744db3e663254ae42c752b74 (patch) | |
tree | ffdf59ff9c31b522b47fd5d169b6d518a628abce /src | |
parent | 92e75480e2e6aa32318b654aeb59315fecf27ea9 (diff) | |
download | ghdl-6448431a20876b11744db3e663254ae42c752b74.tar.gz ghdl-6448431a20876b11744db3e663254ae42c752b74.tar.bz2 ghdl-6448431a20876b11744db3e663254ae42c752b74.zip |
synth: rename get/set_module for instances.
Diffstat (limited to 'src')
-rw-r--r-- | src/synth/synth-context.adb | 8 | ||||
-rw-r--r-- | src/synth/synth-context.ads | 6 | ||||
-rw-r--r-- | src/synth/synth-insts.adb | 30 | ||||
-rw-r--r-- | src/synth/synth-stmts.adb | 2 | ||||
-rw-r--r-- | src/synth/synthesis.adb | 2 |
5 files changed, 23 insertions, 25 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb index 99dd2cce5..3a57912f1 100644 --- a/src/synth/synth-context.adb +++ b/src/synth/synth-context.adb @@ -93,15 +93,15 @@ package body Synth.Context is Deallocate (Synth_Inst); end Free_Instance; - procedure Set_Module (Inst : Synth_Instance_Acc; M : Module) is + procedure Set_Instance_Module (Inst : Synth_Instance_Acc; M : Module) is begin Inst.M := M; - end Set_Module; + end Set_Instance_Module; - function Get_Module (Inst : Synth_Instance_Acc) return Module is + function Get_Instance_Module (Inst : Synth_Instance_Acc) return Module is begin return Inst.M; - end Get_Module; + end Get_Instance_Module; function Get_Sname (Inst : Synth_Instance_Acc) return Sname is begin diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads index 390141468..9ea00782c 100644 --- a/src/synth/synth-context.ads +++ b/src/synth/synth-context.ads @@ -51,9 +51,9 @@ package Synth.Context is function Get_Sname (Inst : Synth_Instance_Acc) return Sname; pragma Inline (Get_Sname); - procedure Set_Module (Inst : Synth_Instance_Acc; M : Module); - function Get_Module (Inst : Synth_Instance_Acc) return Module; - pragma Inline (Set_Module, Get_Module); + procedure Set_Instance_Module (Inst : Synth_Instance_Acc; M : Module); + function Get_Instance_Module (Inst : Synth_Instance_Acc) return Module; + pragma Inline (Get_Instance_Module); procedure Create_Object (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc); diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 522c5d182..223245601 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -217,11 +217,10 @@ package body Synth.Insts is end loop; -- Declare module. - Set_Module (Syn_Inst, - New_User_Module - (Get_Module (Root_Instance), - New_Sname_User (Get_Identifier (Decl)), - Id_User_None, Nbr_Inputs, Nbr_Outputs, 0)); + Set_Instance_Module + (Syn_Inst, New_User_Module (Get_Instance_Module (Root_Instance), + New_Sname_User (Get_Identifier (Decl)), + Id_User_None, Nbr_Inputs, Nbr_Outputs, 0)); -- Add ports to module. declare @@ -245,7 +244,7 @@ package body Synth.Insts is end loop; pragma Assert (Nbr_Inputs = Inports'Last); pragma Assert (Nbr_Outputs = Outports'Last); - Set_Port_Desc (Get_Module (Syn_Inst), Inports, Outports); + Set_Port_Desc (Get_Instance_Module (Syn_Inst), Inports, Outports); end; return Inst_Object'(Decl => Decl, @@ -370,9 +369,9 @@ package body Synth.Insts is -- TODO: free sub_inst. - Inst := New_Instance - (Get_Module (Syn_Inst), Get_Module (Inst_Obj.Syn_Inst), - New_Sname_User (Get_Identifier (Stmt))); + Inst := New_Instance (Get_Instance_Module (Syn_Inst), + Get_Instance_Module (Inst_Obj.Syn_Inst), + New_Sname_User (Get_Identifier (Stmt))); Synth_Instantiate_Module (Syn_Inst, Inst, Inst_Obj, Get_Port_Map_Aspect_Chain (Stmt)); @@ -542,9 +541,9 @@ package body Synth.Insts is -- TODO: free sub_inst. - Inst := New_Instance - (Get_Module (Syn_Inst), Get_Module (Inst_Obj.Syn_Inst), - New_Sname_User (Get_Identifier (Stmt))); + Inst := New_Instance (Get_Instance_Module (Syn_Inst), + Get_Instance_Module (Inst_Obj.Syn_Inst), + New_Sname_User (Get_Identifier (Stmt))); Synth_Instantiate_Module (Comp_Inst, Inst, Inst_Obj, Get_Port_Map_Aspect_Chain (Bind)); @@ -774,8 +773,8 @@ package body Synth.Insts is return; end if; - Self_Inst := Create_Self_Instance (Get_Module (Syn_Inst)); - Builders.Set_Parent (Build_Context, Get_Module (Syn_Inst)); + Self_Inst := Create_Self_Instance (Get_Instance_Module (Syn_Inst)); + Builders.Set_Parent (Build_Context, Get_Instance_Module (Syn_Inst)); -- Create wires for inputs and outputs. Inter := Get_Port_Chain (Entity); @@ -816,7 +815,8 @@ package body Synth.Insts is -- a correctness point: there might be some unsynthesizable gates, like -- the one created for 'rising_egde (clk) and not rst'. if not Flags.Flag_Debug_Nocleanup then - Netlists.Utils.Remove_Unused_Instances (Get_Module (Syn_Inst)); + Netlists.Utils.Remove_Unused_Instances + (Get_Instance_Module (Syn_Inst)); end if; end Synth_Instance; diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index 6d023c5e2..ddef62a74 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -1828,8 +1828,6 @@ package body Synth.Stmts is begin Bod_Sname := New_Sname (Get_Sname (Syn_Inst), Get_Identifier (Bod)); Bod_Inst := Make_Instance (Syn_Inst, Bod, Bod_Sname); - -- Same module. - Set_Module (Bod_Inst, Get_Module (Syn_Inst)); Mark (M, Proc_Pool); Instance_Pool := Proc_Pool'Access; diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb index fadf6e69a..f847105aa 100644 --- a/src/synth/synthesis.adb +++ b/src/synth/synthesis.adb @@ -142,6 +142,6 @@ package body Synthesis is raise Compilation_Error; end if; - M := Get_Module (Global_Instance); + M := Get_Instance_Module (Global_Instance); end Synth_Design; end Synthesis; |