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author | Tristan Gingold <tgingold@free.fr> | 2019-08-31 07:15:30 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-08-31 07:15:30 +0200 |
commit | 6daefbc5e6ffc2da14cca618fd8207e04dff665b (patch) | |
tree | 6284bb41f473145f352dc579ca13ae3bf06e9404 /src | |
parent | a14e0e60f448526f6ee4dc2bb2a524a8cd324f6f (diff) | |
download | ghdl-6daefbc5e6ffc2da14cca618fd8207e04dff665b.tar.gz ghdl-6daefbc5e6ffc2da14cca618fd8207e04dff665b.tar.bz2 ghdl-6daefbc5e6ffc2da14cca618fd8207e04dff665b.zip |
synth: elab subprogram interfaces subtype
Diffstat (limited to 'src')
-rw-r--r-- | src/synth/synth-decls.adb | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 691c32aa1..2382558bd 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -411,6 +411,18 @@ package body Synth.Decls is end loop; end Synth_Attribute_Specification; + procedure Synth_Subprogram_Declaration + (Syn_Inst : Synth_Instance_Acc; Subprg : Node) + is + Inter : Node; + begin + Inter := Get_Interface_Declaration_Chain (Subprg); + while Inter /= Null_Node loop + Synth_Declaration_Type (Syn_Inst, Inter); + Inter := Get_Chain (Inter); + end loop; + end Synth_Subprogram_Declaration; + procedure Synth_Declaration (Syn_Inst : Synth_Instance_Acc; Decl : Node) is begin case Get_Kind (Decl) is @@ -457,8 +469,7 @@ package body Synth.Decls is Create_Var_Wire (Syn_Inst, Decl, null); when Iir_Kind_Procedure_Declaration | Iir_Kind_Function_Declaration => - -- TODO: elaborate interfaces - null; + Synth_Subprogram_Declaration (Syn_Inst, Decl); when Iir_Kind_Procedure_Body | Iir_Kind_Function_Body => null; |