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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-09 19:05:40 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-10 07:48:51 +0100 |
| commit | 7286838d5caaa764c7201c82fe390483ef5c5661 (patch) | |
| tree | f920c3bea4ad69c91468e52fb724d396c3696062 /src | |
| parent | 94166c9a2cdef18cdb3da9797d77ddd156c070b8 (diff) | |
| download | ghdl-7286838d5caaa764c7201c82fe390483ef5c5661.tar.gz ghdl-7286838d5caaa764c7201c82fe390483ef5c5661.tar.bz2 ghdl-7286838d5caaa764c7201c82fe390483ef5c5661.zip | |
synth-vhdl_aggr: optimize common aggregate
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 14 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_aggr.adb | 41 |
2 files changed, 38 insertions, 17 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 849553d01..423862f6e 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -157,12 +157,14 @@ package body Simul.Vhdl_Elab is if E.Kind in Mode_Signal_User then if E.Typ.W > 0 then - E.Nbr_Sources := - new Nbr_Sources_Array'(0 .. E.Typ.W - 1 => - (Nbr_Drivers => 0, - Nbr_Conns => 0, - Total => 0, - Last_Proc => No_Process_Index)); + E.Nbr_Sources := new Nbr_Sources_Array (0 .. E.Typ.W - 1); + -- Avoid aggregate to avoid stack overflow. + for I in E.Nbr_Sources'Range loop + E.Nbr_Sources (I) := (Nbr_Drivers => 0, + Nbr_Conns => 0, + Total => 0, + Last_Proc => No_Process_Index); + end loop; Mark_Resolved_Signals (0, Get_Type (E.Decl), E.Typ, E.Nbr_Sources.all, False); diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb index 8bb3b4b82..533dedf05 100644 --- a/src/synth/synth-vhdl_aggr.adb +++ b/src/synth/synth-vhdl_aggr.adb @@ -132,6 +132,23 @@ package body Synth.Vhdl_Aggr is Nbr_Els : Nat32; Sub_Err : Boolean; + function Synth_Single_Value return Valtyp + is + Val : Valtyp; + begin + Val := Synth_Expression_With_Type (Syn_Inst, Value, El_Typ); + Val := Synth_Subtype_Conversion + (Syn_Inst, Val, El_Typ, False, Value); + if Val = No_Valtyp then + Err_P := True; + else + if Const_P and then not Is_Static (Val.Val) then + Const_P := False; + end if; + end if; + return Val; + end Synth_Single_Value; + procedure Set_Elem (Pos : Nat32) is Sub_Const : Boolean; @@ -142,18 +159,9 @@ package body Synth.Vhdl_Aggr is if Typ.Alast then pragma Assert (Dim = Strides'Last); - Val := Synth_Expression_With_Type (Syn_Inst, Value, El_Typ); - Val := Synth_Subtype_Conversion - (Syn_Inst, Val, El_Typ, False, Value); + Val := Synth_Single_Value; pragma Assert (Res (Pos) = No_Valtyp); Res (Pos) := Val; - if Val = No_Valtyp then - Err_P := True; - else - if Const_P and then not Is_Static (Val.Val) then - Const_P := False; - end if; - end if; else Fill_Array_Aggregate (Syn_Inst, Value, Res, El_Typ, Pos, Strides, Dim + 1, @@ -252,12 +260,23 @@ package body Synth.Vhdl_Aggr is declare Last_Pos : constant Nat32 := First_Pos + Nat32 (Bound.Len) * Stride; + Is_Static : constant Boolean := Typ.Alast + and then Get_Expr_Staticness (Value) >= Globally; + Val : Valtyp; begin + if Is_Static then + Val := Synth_Single_Value; + end if; while Pos < Last_Pos loop if Res (Pos) = No_Valtyp then -- FIXME: the check is not correct if there is -- an array. - Set_Elem (Pos); + if Is_Static then + Nbr_Els := Nbr_Els + 1; + Res (Pos) := Val; + else + Set_Elem (Pos); + end if; end if; Pos := Pos + Stride; end loop; |