vhdl: recognize to_integer/to_signed/to_unsigned.

4 files changed, 66 insertions, 1 deletions

diff --git a/src/std_names.adb b/src/std_names.adb
index 7628e6407..f19556bc1 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -622,6 +622,9 @@ package body Std_Names is
       Def ("std_logic_signed",   Name_Std_Logic_Signed);
       Def ("std_logic_textio",   Name_Std_Logic_Textio);
       Def ("std_logic_unsigned", Name_Std_Logic_Unsigned);
+      Def ("to_integer",         Name_To_Integer);
+      Def ("to_unsigned",        Name_To_Unsigned);
+      Def ("to_signed",          Name_To_Signed);
 
       --  Verilog directives
       Def ("define",          Name_Define);
diff --git a/src/std_names.ads b/src/std_names.ads
index 0f9a1100a..de5af8131 100644
--- a/src/std_names.ads
+++ b/src/std_names.ads
@@ -705,7 +705,10 @@ package Std_Names is
    Name_Std_Logic_Signed   : constant Name_Id := Name_First_Ieee + 016;
    Name_Std_Logic_Textio   : constant Name_Id := Name_First_Ieee + 017;
    Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 018;
-   Name_Last_Ieee          : constant Name_Id := Name_Std_Logic_Unsigned;
+   Name_To_Integer         : constant Name_Id := Name_First_Ieee + 019;
+   Name_To_Unsigned        : constant Name_Id := Name_First_Ieee + 020;
+   Name_To_Signed          : constant Name_Id := Name_First_Ieee + 021;
+   Name_Last_Ieee          : constant Name_Id := Name_To_Signed;
 
    --  Verilog Directives.
    Name_First_Directive : constant Name_Id := Name_Last_Ieee + 1;
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index 773a41770..e01eb8ec7 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -183,6 +183,52 @@ package body Vhdl.Ieee.Numeric is
          Set_Implicit_Definition (Decl, Pats (Pkg, Arg1_Sign));
       end Handle_Unary;
 
+      procedure Handle_To_Unsigned is
+      begin
+         if Arg1_Kind = Arg_Scal and Arg1_Sign = Type_Unsigned then
+            if Arg2_Kind = Arg_Scal and Arg2_Sign = Type_Unsigned then
+               Set_Implicit_Definition
+                 (Decl, Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns);
+            elsif Arg2_Kind = Arg_Vect and Arg2_Sign = Type_Unsigned then
+               Set_Implicit_Definition
+                 (Decl, Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Uns_Uns);
+            else
+               raise Error;
+            end if;
+         else
+            raise Error;
+         end if;
+      end Handle_To_Unsigned;
+
+      procedure Handle_To_Signed is
+      begin
+         if Arg1_Kind = Arg_Scal and Arg1_Sign = Type_Signed then
+            if Arg2_Kind = Arg_Scal and Arg2_Sign = Type_Unsigned then
+               Set_Implicit_Definition
+                 (Decl, Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn);
+            elsif Arg2_Kind = Arg_Vect and Arg2_Sign = Type_Signed then
+               Set_Implicit_Definition
+                 (Decl, Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn);
+            else
+               raise Error;
+            end if;
+         else
+            raise Error;
+         end if;
+      end Handle_To_Signed;
+
+      procedure Handle_To_Integer is
+      begin
+         if Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Unsigned then
+            Set_Implicit_Definition
+              (Decl, Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat);
+         elsif Arg1_Kind = Arg_Vect and Arg1_Sign = Type_Signed then
+            Set_Implicit_Definition
+              (Decl, Iir_Predefined_Ieee_Numeric_Std_Toint_Sgn_Int);
+         else
+            raise Error;
+         end if;
+      end Handle_To_Integer;
    begin
       Decl := Get_Declaration_Chain (Pkg_Decl);
 
@@ -263,6 +309,10 @@ package body Vhdl.Ieee.Numeric is
                        | Name_To_Ostring
                        | Name_To_Hstring =>
                         null;
+                     when Name_To_Unsigned =>
+                        Handle_To_Unsigned;
+                     when Name_To_Signed =>
+                        Handle_To_Signed;
                      when others =>
                         null;
                   end case;
@@ -271,6 +321,8 @@ package body Vhdl.Ieee.Numeric is
                   case Get_Identifier (Decl) is
                      when Name_Op_Minus =>
                         Handle_Unary (Neg_Patterns);
+                     when Name_To_Integer =>
+                        Handle_To_Integer;
                      when others =>
                         null;
                   end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 6518fd7ef..f86047f93 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4808,6 +4808,13 @@ package Vhdl.Nodes is
       --  Numeric_Std.
       --  Abbreviations:
       --  Uns: Unsigned, Sgn: Signed, Nat: Natural, Int: Integer.
+      Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat,
+      Iir_Predefined_Ieee_Numeric_Std_Toint_Sgn_Int,
+      Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Uns_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Sgn_Sgn,
+
       Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
       Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
       Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,