vpi: handle parameters/generics.

5 files changed, 251 insertions, 248 deletions

diff --git a/src/grt/grt-fst.adb b/src/grt/grt-fst.adb
index 98403b69e..483eadd15 100644
--- a/src/grt/grt-fst.adb
+++ b/src/grt/grt-fst.adb
@@ -137,7 +137,9 @@ package body Grt.Fst is
 
       --  Compare signals.
       for I in 1 .. Len loop
-         if Left.Sigs (I - 1) /= Right.Sigs (I - 1) then
+         if To_Signal_Arr_Ptr (Left.Ptr)(I - 1)
+           /= To_Signal_Arr_Ptr (Right.Ptr)(I - 1)
+         then
             return False;
          end if;
       end loop;
@@ -153,7 +155,7 @@ package body Grt.Fst is
       Res := Vcd_Var_Type'Pos (El.Vtype) * 2 + Vcd_Value_Kind'Pos (El.Val);
       Res := Res + Len * 29;
       for I in 1 .. Len loop
-         Iaddr := To_Integer (El.Sigs (I - 1).all'Address);
+         Iaddr := To_Integer (To_Signal_Arr_Ptr (El.Ptr)(I - 1).all'Address);
          Res := Res +
            Ghdl_Index_Type (Iaddr mod Integer_Address (Ghdl_Index_Type'Last));
       end loop;
@@ -542,73 +544,37 @@ package body Grt.Fst is
       V : Fst_Sig_Info renames Fst_Table.Table (I);
       Len : constant Ghdl_Index_Type := Get_Wire_Length (V.Wire);
       Hand : constant fstHandle := V.Hand;
-      Sig : constant Signal_Arr_Ptr := V.Wire.Sigs;
    begin
-      case V.Wire.Val is
-         when Vcd_Effective =>
-            case V.Wire.Vtype is
-               when Vcd_Bit
-                 | Vcd_Bool
-                 | Vcd_Bitvector =>
-                  declare
-                     Str : Std_String_Uncons (0 .. Len - 1);
-                  begin
-                     for I in Str'Range loop
-                        Str (I) := From_Bit (Sig (I).Value_Ptr.B1);
-                     end loop;
-                     fstWriterEmitValueChange (Context, Hand, Str'Address);
-                  end;
-               when Vcd_Stdlogic
-                 | Vcd_Stdlogic_Vector =>
-                  declare
-                     Str : Std_String_Uncons (0 .. Len - 1);
-                  begin
-                     for I in Str'Range loop
-                        Str (I) := From_Std (Sig (I).Value_Ptr.E8);
-                     end loop;
-                     fstWriterEmitValueChange (Context, Hand, Str'Address);
-                  end;
-               when Vcd_Integer32 =>
-                  Fst_Put_Integer32 (Hand, Sig (0).Value_Ptr.E32);
-               when Vcd_Float64 =>
-                  null;
-               when Vcd_Enum8 =>
-                  Fst_Put_Enum8 (Hand, Sig (0).Value_Ptr.E8, V.Wire.Rti);
-               when Vcd_Bad =>
-                  null;
-            end case;
-         when Vcd_Driving =>
-            case V.Wire.Vtype is
-               when Vcd_Bit
-                 | Vcd_Bool
-                 | Vcd_Bitvector =>
-                  declare
-                     Str : Std_String_Uncons (0 .. Len - 1);
-                  begin
-                     for I in Str'Range loop
-                        Str (I) := From_Bit (Sig (I).Driving_Value.B1);
-                     end loop;
-                     fstWriterEmitValueChange (Context, Hand, Str'Address);
-                  end;
-               when Vcd_Stdlogic
-                 | Vcd_Stdlogic_Vector =>
-                  declare
-                     Str : Std_String_Uncons (0 .. Len - 1);
-                  begin
-                     for I in Str'Range loop
-                        Str (I) := From_Std (Sig (I).Driving_Value.E8);
-                     end loop;
-                     fstWriterEmitValueChange (Context, Hand, Str'Address);
-                  end;
-               when Vcd_Integer32 =>
-                  Fst_Put_Integer32 (Hand, Sig (0).Driving_Value.E32);
-               when Vcd_Float64 =>
-                  null;
-               when Vcd_Enum8 =>
-                  Fst_Put_Enum8 (Hand, Sig (0).Driving_Value.E8, V.Wire.Rti);
-               when Vcd_Bad =>
-                  null;
-            end case;
+      case V.Wire.Vtype is
+         when Vcd_Bit
+           | Vcd_Bool
+           | Vcd_Bitvector =>
+            declare
+               Str : Std_String_Uncons (0 .. Len - 1);
+            begin
+               for I in Str'Range loop
+                  Str (I) := From_Bit (Verilog_Wire_Val (V.Wire, I).B1);
+               end loop;
+               fstWriterEmitValueChange (Context, Hand, Str'Address);
+            end;
+         when Vcd_Stdlogic
+           | Vcd_Stdlogic_Vector =>
+            declare
+               Str : Std_String_Uncons (0 .. Len - 1);
+            begin
+               for I in Str'Range loop
+                  Str (I) := From_Std (Verilog_Wire_Val (V.Wire, I).E8);
+               end loop;
+               fstWriterEmitValueChange (Context, Hand, Str'Address);
+            end;
+         when Vcd_Integer32 =>
+            Fst_Put_Integer32 (Hand, Verilog_Wire_Val (V.Wire).E32);
+         when Vcd_Float64 =>
+            null;
+         when Vcd_Enum8 =>
+            Fst_Put_Enum8 (Hand, Verilog_Wire_Val (V.Wire).E8, V.Wire.Rti);
+         when Vcd_Bad =>
+            null;
       end case;
    end Fst_Put_Var;
 
diff --git a/src/grt/grt-vcd.adb b/src/grt/grt-vcd.adb
index d7b223a16..6c81ec7b1 100644
--- a/src/grt/grt-vcd.adb
+++ b/src/grt/grt-vcd.adb
@@ -26,8 +26,6 @@
 with System; use System;
 with Interfaces;
 with Grt.Stdio; use Grt.Stdio;
-with System.Storage_Elements; --  Work around GNAT bug.
-pragma Unreferenced (System.Storage_Elements);
 with Grt.Errors; use Grt.Errors;
 with Grt.Signals; use Grt.Signals;
 with Grt.Table;
@@ -314,7 +312,6 @@ package body Grt.Vcd is
       Sig_Addr : Address;
 
       Kind : Vcd_Var_Type;
-      Sigs : Grt.Signals.Signal_Arr_Ptr;
       Irange : Ghdl_Range_Ptr;
       Val : Vcd_Value_Kind;
    begin
@@ -338,14 +335,12 @@ package body Grt.Vcd is
            | Ghdl_Rtik_Type_E8
            | Ghdl_Rtik_Subtype_Scalar =>
             Kind := Rti_To_Vcd_Kind (Rti);
-            Sigs := To_Signal_Arr_Ptr (Sig_Addr);
          when Ghdl_Rtik_Subtype_Array =>
             declare
                St : Ghdl_Rtin_Subtype_Array_Acc;
             begin
                St := To_Ghdl_Rtin_Subtype_Array_Acc (Rti);
                Kind := Rti_To_Vcd_Kind (St.Basetype);
-               Sigs := To_Signal_Arr_Ptr (Sig_Addr);
                Irange := To_Ghdl_Range_Ptr
                  (Loc_To_Addr (St.Common.Depth, St.Bounds,
                                Avhpi_Get_Context (Sig)));
@@ -356,7 +351,7 @@ package body Grt.Vcd is
             begin
                Kind := Rti_To_Vcd_Kind (To_Ghdl_Rtin_Type_Array_Acc (Rti));
                Uc := To_Ghdl_Uc_Array_Acc (Sig_Addr);
-               Sigs := To_Signal_Arr_Ptr (Uc.Base);
+               Sig_Addr := Uc.Base;
                Irange := To_Ghdl_Range_Ptr (Uc.Bounds);
             end;
          when others =>
@@ -365,45 +360,52 @@ package body Grt.Vcd is
 
       --  Do not allow null-array.
       if Irange /= null and then Irange.I32.Len = 0 then
-         Info := (Vtype => Vcd_Bad, Val => Vcd_Effective, Sigs => null);
+         Info := (Vtype => Vcd_Bad, Val => Vcd_Effective, Ptr => Null_Address);
          return;
       end if;
 
-      if Vhpi_Get_Kind (Sig) = VhpiPortDeclK then
-         case Vhpi_Get_Mode (Sig) is
-            when VhpiInMode
-              | VhpiInoutMode
-              | VhpiBufferMode
-              | VhpiLinkageMode =>
-               Val := Vcd_Effective;
-            when VhpiOutMode =>
-               Val := Vcd_Driving;
-            when VhpiErrorMode =>
-               Kind := Vcd_Bad;
-         end case;
-      else
-         Val := Vcd_Effective;
-      end if;
+      case Vhpi_Get_Kind (Sig) is
+         when VhpiPortDeclK =>
+            case Vhpi_Get_Mode (Sig) is
+               when VhpiInMode
+                 | VhpiInoutMode
+                 | VhpiBufferMode
+                 | VhpiLinkageMode =>
+                  Val := Vcd_Effective;
+               when VhpiOutMode =>
+                  Val := Vcd_Driving;
+               when VhpiErrorMode =>
+                  Kind := Vcd_Bad;
+            end case;
+         when VhpiSigDeclK =>
+            Val := Vcd_Effective;
+         when VhpiGenericDeclK =>
+            Val := Vcd_Variable;
+         when others =>
+            Info := (Vtype => Vcd_Bad,
+                     Val => Vcd_Effective, Ptr => Null_Address);
+            return;
+      end case;
 
       case Kind is
          when Vcd_Bad =>
-            Info := (Vcd_Bad, Vcd_Effective, null);
+            Info := (Vcd_Bad, Vcd_Effective, Null_Address);
          when Vcd_Enum8 =>
-            Info := (Vcd_Enum8, Val, Sigs, Rti);
+            Info := (Vcd_Enum8, Val, Sig_Addr, Rti);
          when Vcd_Bool =>
-            Info := (Vcd_Bool, Val, Sigs);
+            Info := (Vcd_Bool, Val, Sig_Addr);
          when Vcd_Integer32 =>
-            Info := (Vcd_Integer32, Val, Sigs);
+            Info := (Vcd_Integer32, Val, Sig_Addr);
          when Vcd_Float64 =>
-            Info := (Vcd_Float64, Val, Sigs);
+            Info := (Vcd_Float64, Val, Sig_Addr);
          when Vcd_Bit =>
-            Info := (Vcd_Bit, Val, Sigs);
+            Info := (Vcd_Bit, Val, Sig_Addr);
          when Vcd_Stdlogic =>
-            Info := (Vcd_Stdlogic, Val, Sigs);
+            Info := (Vcd_Stdlogic, Val, Sig_Addr);
          when Vcd_Bitvector =>
-            Info := (Vcd_Bitvector, Val, Sigs, Irange);
+            Info := (Vcd_Bitvector, Val, Sig_Addr, Irange);
          when Vcd_Stdlogic_Vector =>
-            Info := (Vcd_Stdlogic_Vector, Val, Sigs, Irange);
+            Info := (Vcd_Stdlogic_Vector, Val, Sig_Addr, Irange);
       end case;
    end Get_Verilog_Wire;
 
@@ -417,6 +419,33 @@ package body Grt.Vcd is
       end if;
    end Get_Wire_Length;
 
+   function Verilog_Wire_Val (Info : Verilog_Wire_Info)
+                             return Ghdl_Value_Ptr is
+   begin
+      case Info.Val is
+         when Vcd_Effective =>
+            return To_Signal_Arr_Ptr (Info.Ptr)(0).Value_Ptr;
+         when Vcd_Driving =>
+            return To_Signal_Arr_Ptr (Info.Ptr)(0).Driving_Value'Access;
+         when Vcd_Variable =>
+            return To_Ghdl_Value_Ptr (Info.Ptr);
+      end case;
+   end Verilog_Wire_Val;
+
+   function Verilog_Wire_Val (Info : Verilog_Wire_Info; Idx : Ghdl_Index_Type)
+                             return Ghdl_Value_Ptr is
+   begin
+      case Info.Val is
+         when Vcd_Effective =>
+            return To_Signal_Arr_Ptr (Info.Ptr)(Idx).Value_Ptr;
+         when Vcd_Driving =>
+            return To_Signal_Arr_Ptr (Info.Ptr)(Idx).Driving_Value'Access;
+         when Vcd_Variable =>
+            --  TODO
+            Internal_Error ("verilog_wire_val");
+      end case;
+   end Verilog_Wire_Val;
+
    procedure Add_Signal (Sig : VhpiHandleT)
    is
       N : Vcd_Index_Type;
@@ -479,6 +508,8 @@ package body Grt.Vcd is
                   Vcd_Put ("effective ");
                when Vcd_Driving =>
                   Vcd_Put ("driving ");
+               when Vcd_Variable =>
+                  Vcd_Put ("variable ");
             end case;
             Vcd_Put_End;
          end if;
@@ -685,92 +716,59 @@ package body Grt.Vcd is
       V : Verilog_Wire_Info renames Vcd_Table.Table (I);
       Len : constant Ghdl_Index_Type := Get_Wire_Length (V);
    begin
-      case V.Val is
-         when Vcd_Effective =>
-            case V.Vtype is
-               when Vcd_Bit
-                 | Vcd_Bool =>
-                  Vcd_Put_Bit (V.Sigs (0).Value_Ptr.B1);
-               when Vcd_Stdlogic =>
-                  Vcd_Put_Stdlogic (V.Sigs (0).Value_Ptr.E8);
-               when Vcd_Integer32 =>
-                  Vcd_Putc ('b');
-                  Vcd_Put_Integer32 (V.Sigs (0).Value_Ptr.E32);
-                  Vcd_Putc (' ');
-               when Vcd_Float64 =>
-                  Vcd_Putc ('r');
-                  Vcd_Put_Float64 (V.Sigs (0).Value_Ptr.F64);
-                  Vcd_Putc (' ');
-               when Vcd_Bitvector =>
-                  Vcd_Putc ('b');
-                  for J in 0 .. Len - 1 loop
-                     Vcd_Put_Bit (V.Sigs (J).Value_Ptr.B1);
-                  end loop;
-                  Vcd_Putc (' ');
-               when Vcd_Stdlogic_Vector =>
-                  Vcd_Putc ('b');
-                  for J in 0 .. Len - 1 loop
-                     Vcd_Put_Stdlogic (V.Sigs (J).Value_Ptr.E8);
-                  end loop;
-                  Vcd_Putc (' ');
-               when Vcd_Bad
-                 | Vcd_Enum8 =>
-                  null;
-            end case;
-         when Vcd_Driving =>
-            case V.Vtype is
-               when Vcd_Bit
-                 | Vcd_Bool =>
-                  Vcd_Put_Bit (V.Sigs (0).Driving_Value.B1);
-               when Vcd_Stdlogic =>
-                  Vcd_Put_Stdlogic (V.Sigs (0).Driving_Value.E8);
-               when Vcd_Integer32 =>
-                  Vcd_Putc ('b');
-                  Vcd_Put_Integer32 (V.Sigs (0).Driving_Value.E32);
-                  Vcd_Putc (' ');
-               when Vcd_Float64 =>
-                  Vcd_Putc ('r');
-                  Vcd_Put_Float64 (V.Sigs (0).Driving_Value.F64);
-                  Vcd_Putc (' ');
-               when Vcd_Bitvector =>
-                  Vcd_Putc ('b');
-                  for J in 0 .. Len - 1 loop
-                     Vcd_Put_Bit (V.Sigs (J).Driving_Value.B1);
-                  end loop;
-                  Vcd_Putc (' ');
-               when Vcd_Stdlogic_Vector =>
-                  Vcd_Putc ('b');
-                  for J in 0 .. Len - 1 loop
-                     Vcd_Put_Stdlogic (V.Sigs (J).Driving_Value.E8);
-                  end loop;
-                  Vcd_Putc (' ');
-               when Vcd_Bad
-                 | Vcd_Enum8 =>
-                  null;
-            end case;
+      case V.Vtype is
+         when Vcd_Bit
+           | Vcd_Bool =>
+            Vcd_Put_Bit (Verilog_Wire_Val (V).B1);
+         when Vcd_Stdlogic =>
+            Vcd_Put_Stdlogic (Verilog_Wire_Val (V).E8);
+         when Vcd_Integer32 =>
+            Vcd_Putc ('b');
+            Vcd_Put_Integer32 (Verilog_Wire_Val (V).E32);
+            Vcd_Putc (' ');
+         when Vcd_Float64 =>
+            Vcd_Putc ('r');
+            Vcd_Put_Float64 (Verilog_Wire_Val (V).F64);
+            Vcd_Putc (' ');
+         when Vcd_Bitvector =>
+            Vcd_Putc ('b');
+            for J in 0 .. Len - 1 loop
+               Vcd_Put_Bit (Verilog_Wire_Val (V, J).B1);
+            end loop;
+            Vcd_Putc (' ');
+         when Vcd_Stdlogic_Vector =>
+            Vcd_Putc ('b');
+            for J in 0 .. Len - 1 loop
+               Vcd_Put_Stdlogic (Verilog_Wire_Val (V, J).E8);
+            end loop;
+            Vcd_Putc (' ');
+         when Vcd_Bad
+           | Vcd_Enum8 =>
+            null;
       end case;
       Vcd_Put_Idcode (I);
       Vcd_Newline;
    end Vcd_Put_Var;
 
    function Verilog_Wire_Changed (Info : Verilog_Wire_Info; Last : Std_Time)
-                                 return Boolean
-   is
-      Len : constant Ghdl_Index_Type := Get_Wire_Length (Info);
+                                 return Boolean is
    begin
-      case Info.Val is
+      case Vcd_Value_Signals (Info.Val) is
          when Vcd_Effective =>
             case Info.Vtype is
                when Vcd_Bit
                  | Vcd_Bool
                  | Vcd_Enum8
                  | Vcd_Stdlogic
-                 | Vcd_Bitvector
-                 | Vcd_Stdlogic_Vector
                  | Vcd_Integer32
                  | Vcd_Float64 =>
-                  for J in 0 .. Len - 1 loop
-                     if Info.Sigs (J).Last_Event = Last then
+                  if To_Signal_Arr_Ptr (Info.Ptr)(0).Last_Event = Last then
+                     return True;
+                  end if;
+               when Vcd_Bitvector
+                 | Vcd_Stdlogic_Vector =>
+                  for J in 0 .. Info.Irange.I32.Len - 1 loop
+                     if To_Signal_Arr_Ptr (Info.Ptr)(J).Last_Event = Last then
                         return True;
                      end if;
                   end loop;
@@ -783,12 +781,15 @@ package body Grt.Vcd is
                  | Vcd_Bool
                  | Vcd_Enum8
                  | Vcd_Stdlogic
-                 | Vcd_Bitvector
-                 | Vcd_Stdlogic_Vector
                  | Vcd_Integer32
                  | Vcd_Float64 =>
-                  for J in 0 .. Len - 1 loop
-                     if Info.Sigs (J).Last_Active = Last then
+                  if To_Signal_Arr_Ptr (Info.Ptr)(0).Last_Active = Last then
+                     return True;
+                  end if;
+               when Vcd_Bitvector
+                 | Vcd_Stdlogic_Vector =>
+                  for J in 0 .. Info.Irange.I32.Len - 1 loop
+                     if To_Signal_Arr_Ptr (Info.Ptr)(J).Last_Active = Last then
                         return True;
                      end if;
                   end loop;
@@ -799,21 +800,22 @@ package body Grt.Vcd is
       return False;
    end Verilog_Wire_Changed;
 
-   function Verilog_Wire_Event (Info : Verilog_Wire_Info) return Boolean
-   is
-      Len : constant Ghdl_Index_Type := Get_Wire_Length (Info);
+   function Verilog_Wire_Event (Info : Verilog_Wire_Info) return Boolean is
    begin
       case Info.Vtype is
          when Vcd_Bit
            | Vcd_Bool
            | Vcd_Enum8
            | Vcd_Stdlogic
-           | Vcd_Bitvector
-           | Vcd_Stdlogic_Vector
            | Vcd_Integer32
            | Vcd_Float64 =>
-            for J in 0 .. Len - 1 loop
-               if Info.Sigs (J).Event then
+            if To_Signal_Arr_Ptr (Info.Ptr)(0).Event then
+               return True;
+            end if;
+         when Vcd_Bitvector
+           | Vcd_Stdlogic_Vector =>
+            for J in 0 .. Info.Irange.I32.Len - 1 loop
+               if To_Signal_Arr_Ptr (Info.Ptr)(J).Event then
                   return True;
                end if;
             end loop;
diff --git a/src/grt/grt-vcd.ads b/src/grt/grt-vcd.ads
index 566901dfc..6253a4323 100644
--- a/src/grt/grt-vcd.ads
+++ b/src/grt/grt-vcd.ads
@@ -23,10 +23,10 @@
 --  however invalidate any other reasons why the executable file might be
 --  covered by the GNU Public License.
 
+with System;
 with Grt.Types; use Grt.Types;
 with Grt.Avhpi; use Grt.Avhpi;
 with Grt.Rtis;
-with Grt.Signals;
 
 package Grt.Vcd is
    --  Abstract type for IO.
@@ -67,13 +67,17 @@ package Grt.Vcd is
      range Vcd_Bitvector .. Vcd_Stdlogic_Vector;
 
    --  Which value to be displayed: effective or driving (for out signals).
-   type Vcd_Value_Kind is (Vcd_Effective, Vcd_Driving);
+   type Vcd_Value_Kind is (Vcd_Effective, Vcd_Driving, Vcd_Variable);
+
+   --  For signals.
+   subtype Vcd_Value_Signals is Vcd_Value_Kind
+     range Vcd_Effective .. Vcd_Driving;
 
    type Verilog_Wire_Info (Vtype : Vcd_Var_Type := Vcd_Bad) is record
       Val : Vcd_Value_Kind;
 
-      --  Access to an array of signals.
-      Sigs : Grt.Signals.Signal_Arr_Ptr;
+      --  Access to an array of signals or access to the value.
+      Ptr : System.Address;
 
       case Vtype is
          when Vcd_Var_Vectors =>
@@ -102,5 +106,10 @@ package Grt.Vcd is
    --  Return TRUE if there is an event on the wire, for the current cycle.
    function Verilog_Wire_Event (Info : Verilog_Wire_Info) return Boolean;
 
+   --  Return a pointer to the value of a wire.
+   function Verilog_Wire_Val (Info : Verilog_Wire_Info) return Ghdl_Value_Ptr;
+   function Verilog_Wire_Val (Info : Verilog_Wire_Info; Idx : Ghdl_Index_Type)
+                             return Ghdl_Value_Ptr;
+
    procedure Register;
 end Grt.Vcd;
diff --git a/src/grt/grt-vpi.adb b/src/grt/grt-vpi.adb
index d4a2d2d97..f20cec6f4 100644
--- a/src/grt/grt-vpi.adb
+++ b/src/grt/grt-vpi.adb
@@ -199,6 +199,8 @@ package body Grt.Vpi is
             Trace ("vpiModule");
          when vpiNet =>
             Trace ("vpiNet");
+         when vpiParameter =>
+            Trace ("vpiParameter");
          when vpiScope =>
             Trace ("vpiScope");
          when vpiInternalScope =>
@@ -275,9 +277,13 @@ package body Grt.Vpi is
 
    procedure Trace (Str : Ghdl_C_String) is
    begin
-      Put (Trace_File, '"');
-      Put (Trace_File, Str);
-      Put (Trace_File, '"');
+      if Str = null then
+         Put (Trace_File, "null");
+      else
+         Put (Trace_File, '"');
+         Put (Trace_File, Str);
+         Put (Trace_File, '"');
+      end if;
    end Trace;
 
    procedure Trace_Time (V : Std_Time) is
@@ -418,11 +424,22 @@ package body Grt.Vpi is
       Info : Verilog_Wire_Info;
    begin
       Get_Verilog_Wire (Ref.Ref, Info);
-      if Info.Vtype /= Vcd_Bad then
-         return Natural (Get_Wire_Length (Info));
-      else
-         return 0;
-      end if;
+      case Info.Vtype is
+         when Vcd_Var_Vectors =>
+            return Natural (Get_Wire_Length (Info));
+         when Vcd_Bool
+           | Vcd_Bit
+           | Vcd_Stdlogic =>
+            return 1;
+         when Vcd_Integer32 =>
+            return 32;
+         when Vcd_Enum8 =>
+            return 8;
+         when Vcd_Float64 =>
+            return 0;
+         when Vcd_Bad =>
+            return 0;
+      end case;
    end Vpi_Get_Size;
 
    function Vpi_Get_Vector (Ref : vpiHandle) return Boolean
@@ -501,10 +518,19 @@ package body Grt.Vpi is
                Info : Verilog_Wire_Info;
             begin
                Get_Verilog_Wire (Res, Info);
-               if Info.Kind /= Vcd_Bad then
+               if Info.Vtype /= Vcd_Bad then
                   return vpiNet;
                end if;
             end;
+         when VhpiGenericDeclK =>
+            declare
+               Info : Verilog_Wire_Info;
+            begin
+               Get_Verilog_Wire (Res, Info);
+               if Info.Vtype /= Vcd_Bad then
+                  return vpiParameter;
+               end if;
+            end;
          when others =>
             null;
       end case;
@@ -521,6 +547,9 @@ package body Grt.Vpi is
          when vpiNet =>
             return new struct_vpiHandle'(mType => vpiNet,
                                          Ref => Res);
+         when vpiParameter =>
+            return new struct_vpiHandle'(mType => vpiParameter,
+                                         Ref => Res);
          when others =>
             return null;
       end case;
@@ -755,7 +784,8 @@ package body Grt.Vpi is
    begin
       case Vhpi_Get_Kind (Obj) is
          when VhpiPortDeclK
-           | VhpiSigDeclK =>
+           | VhpiSigDeclK
+           | VhpiGenericDeclK =>
             null;
          when others =>
             return null;
@@ -771,49 +801,36 @@ package body Grt.Vpi is
 
       Reset (Buf_Value); -- reset string buffer
 
-      case Info.Val is
-         when Vcd_Effective =>
-            case Info.Vtype is
-               when Vcd_Bad
-                 | Vcd_Enum8
-                 | Vcd_Integer32
-                 | Vcd_Float64 =>
-                  return null;
-               when Vcd_Bit
-                 | Vcd_Bool
-                 | Vcd_Bitvector =>
-                  for J in 0 .. Len - 1 loop
-                     Append (Buf_Value,
-                             Map_Std_B1 (Info.Sigs (J).Value_Ptr.B1));
-                  end loop;
-               when Vcd_Stdlogic
-                 | Vcd_Stdlogic_Vector =>
-                  for J in 0 .. Len - 1 loop
-                     Append (Buf_Value,
-                             E8_To_Char (Info.Sigs (J).Value_Ptr.E8));
-                  end loop;
-            end case;
-         when Vcd_Driving =>
-            case Info.Vtype is
-               when Vcd_Bad
-                 | Vcd_Enum8
-                 | Vcd_Integer32
-                 | Vcd_Float64 =>
-                  return null;
-               when Vcd_Bit
-                 | Vcd_Bool
-                 | Vcd_Bitvector =>
-                  for J in 0 .. Len - 1 loop
-                     Append (Buf_Value,
-                             Map_Std_B1 (Info.Sigs (J).Driving_Value.B1));
-                  end loop;
-               when Vcd_Stdlogic
-                 | Vcd_Stdlogic_Vector =>
-                  for J in 0 .. Len - 1 loop
-                     Append (Buf_Value,
-                             E8_To_Char (Info.Sigs (J).Driving_Value.E8));
-                  end loop;
-            end case;
+      case Info.Vtype is
+         when Vcd_Bad
+           | Vcd_Enum8
+           | Vcd_Float64 =>
+            return null;
+         when Vcd_Integer32 =>
+            declare
+               V : Ghdl_U32;
+            begin
+               V := Verilog_Wire_Val (Info).E32;
+               for I in 0 .. 31 loop
+                  if (V and 16#8000_0000#) /= 0 then
+                     Append (Buf_Value, '1');
+                  else
+                     Append (Buf_Value, '0');
+                  end if;
+                  V := Shift_Left (V, 1);
+               end loop;
+            end;
+         when Vcd_Bit
+           | Vcd_Bool
+           | Vcd_Bitvector =>
+            for J in 0 .. Len - 1 loop
+               Append (Buf_Value, Map_Std_B1 (Verilog_Wire_Val (Info, J).B1));
+            end loop;
+         when Vcd_Stdlogic
+           | Vcd_Stdlogic_Vector =>
+            for J in 0 .. Len - 1 loop
+               Append (Buf_Value, E8_To_Char (Verilog_Wire_Val (Info, J).E8));
+            end loop;
       end case;
       Append (Buf_Value, NUL);
       return Get_C_String (Buf_Value);
@@ -908,9 +925,13 @@ package body Grt.Vpi is
                begin
                   case Info.Val is
                      when Vcd_Effective =>
-                        Ghdl_Signal_Force_Effective_B1 (Info.Sigs (J), V);
+                        Ghdl_Signal_Force_Effective_B1
+                          (To_Signal_Arr_Ptr (Info.Ptr)(J), V);
                      when Vcd_Driving =>
-                        Ghdl_Signal_Force_Driving_B1 (Info.Sigs (J), V);
+                        Ghdl_Signal_Force_Driving_B1
+                          (To_Signal_Arr_Ptr (Info.Ptr)(J), V);
+                     when Vcd_Variable =>
+                        Verilog_Wire_Val (Info, J).B1 := V;
                   end case;
                end;
             end loop;
@@ -922,9 +943,13 @@ package body Grt.Vpi is
                begin
                   case Info.Val is
                      when Vcd_Effective =>
-                        Ghdl_Signal_Force_Effective_E8 (Info.Sigs (J), V);
+                        Ghdl_Signal_Force_Effective_E8
+                          (To_Signal_Arr_Ptr (Info.Ptr)(J), V);
                      when Vcd_Driving =>
-                        Ghdl_Signal_Force_Driving_E8 (Info.Sigs (J), V);
+                        Ghdl_Signal_Force_Driving_E8
+                          (To_Signal_Arr_Ptr (Info.Ptr)(J), V);
+                     when Vcd_Variable =>
+                        Verilog_Wire_Val (Info, J).E8 := V;
                   end case;
                end;
             end loop;
@@ -1348,8 +1373,8 @@ package body Grt.Vpi is
    end vpi_handle_by_index;
 
    --  Return True iff L and R are equal.  L must not have an element set to
-   --  NUL.
-   function Strcmp (L : String; R : Ghdl_C_String) return Boolean is
+   --  NUL.  R must be lower case.
+   function Strcasecmp (L : String; R : Ghdl_C_String) return Boolean is
    begin
       if L'Last < L'First - 1 then
          --  Handle null string.
@@ -1368,7 +1393,7 @@ package body Grt.Vpi is
 
       --  R is NUL terminated.
       return R (L'Length + 1) = NUL;
-   end Strcmp;
+   end Strcasecmp;
 
    procedure Find_By_Name (Scope : VhpiHandleT;
                            Rel : VhpiOneToManyT;
@@ -1391,7 +1416,7 @@ package body Grt.Vpi is
          exit when Err /= AvhpiErrorOk;
 
          El_Name := Avhpi_Get_Base_Name (Res);
-         exit when Strcmp (Name, El_Name);
+         exit when Strcasecmp (Name, El_Name);
       end loop;
    end Find_By_Name;
 
diff --git a/src/grt/grt-vpi.ads b/src/grt/grt-vpi.ads
index 41dc58e5c..b81d73b58 100644
--- a/src/grt/grt-vpi.ads
+++ b/src/grt/grt-vpi.ads
@@ -44,10 +44,11 @@ package Grt.Vpi is
    -- object codes, see vpi_user.h
    vpiModule:        constant integer := 32;
    vpiNet:           constant integer := 36;
-   vpiScope:         constant integer := 84;
-   vpiInternalScope: constant integer := 92;
+   vpiParameter:     constant integer := 41;
    vpiLeftRange:     constant integer := 79;
    vpiRightRange:    constant integer := 83;
+   vpiScope:         constant integer := 84;
+   vpiInternalScope: constant integer := 92;
 
    vpiStop   : constant := 66;
    vpiFinish : constant := 67;