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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-13 18:43:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-13 18:44:45 +0200 |
| commit | 87435390677f923015ba6a3109dd3c4e397ed462 (patch) | |
| tree | 152bd786f602994929cb434171302651c9658385 /src | |
| parent | fad6dc991dea7a523ab7353a7dde28c71a6a2192 (diff) | |
| download | ghdl-87435390677f923015ba6a3109dd3c4e397ed462.tar.gz ghdl-87435390677f923015ba6a3109dd3c4e397ed462.tar.bz2 ghdl-87435390677f923015ba6a3109dd3c4e397ed462.zip | |
netlists-disp_verilog: do not display blackboxes. Fix #2092
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index baa9db2c0..848adc05b 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -1328,6 +1328,11 @@ package body Netlists.Disp_Verilog is is Self_Inst : constant Instance := Get_Self_Instance (M); begin + if Self_Inst = No_Instance then + -- Blackbox + return; + end if; + -- Module id and name. Put ("module "); Put_Name (Get_Module_Name (M)); |