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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-17 06:11:22 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-17 06:11:22 +0200 |
| commit | 8c55533f130157e826c94a92f55200b916d980f5 (patch) | |
| tree | fce48789ca336f84f177240bb2efb4c04dc83f73 /src | |
| parent | c37e2eb1b423bf22268cda5671618c928150b1ec (diff) | |
| download | ghdl-8c55533f130157e826c94a92f55200b916d980f5.tar.gz ghdl-8c55533f130157e826c94a92f55200b916d980f5.tar.bz2 ghdl-8c55533f130157e826c94a92f55200b916d980f5.zip | |
synth-vhdl_oper: handle to_stdulogicvector for slv. Fix #2062
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index 640a65b77..813a5513d 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1937,6 +1937,7 @@ package body Synth.Vhdl_Oper is when Iir_Predefined_Ieee_1164_To_Bitvector | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv + | Iir_Predefined_Ieee_1164_To_Stdulogicvector_Slv | Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv | Iir_Predefined_Ieee_Numeric_Std_To_01_Uns | Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn |