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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-27 09:56:23 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-27 09:56:23 +0200 |
| commit | ad82dc96d97f0728c8b8f6ab7efa0ab9aa51f469 (patch) | |
| tree | fbc6e0f02777d29130af57bb12493a74e7d70868 /src | |
| parent | 7e766d575ec9fe8f96a5d633ce3de9ba91d53ce3 (diff) | |
| download | ghdl-ad82dc96d97f0728c8b8f6ab7efa0ab9aa51f469.tar.gz ghdl-ad82dc96d97f0728c8b8f6ab7efa0ab9aa51f469.tar.bz2 ghdl-ad82dc96d97f0728c8b8f6ab7efa0ab9aa51f469.zip | |
ghdlsimul: initial stop is after elaboration
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdldrv/ghdlsimul.adb | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb index fd1a13c5a..978d5a501 100644 --- a/src/ghdldrv/ghdlsimul.adb +++ b/src/ghdldrv/ghdlsimul.adb @@ -44,14 +44,11 @@ with Grtlink; with Elab.Vhdl_Context; with Elab.Vhdl_Debug; with Elab.Vhdl_Insts; -with Elab.Debugger; with Synth.Flags; with Simul.Vhdl_Elab; with Simul.Vhdl_Simul; package body Ghdlsimul is - Flag_Interractive : Boolean := False; - procedure Compile_Init (Analyze_Only : Boolean) is begin Common_Compile_Init (Analyze_Only); @@ -102,10 +99,6 @@ package body Ghdlsimul is Simul.Vhdl_Elab.Gather_Processes (Inst); Simul.Vhdl_Elab.Elab_Processes; - if Flag_Interractive then - Elab.Debugger.Debug_Elab (Inst); - end if; - if False then Elab.Vhdl_Debug.Disp_Hierarchy (Inst, False, True); end if; @@ -194,7 +187,7 @@ package body Ghdlsimul is elsif Option = "-t" then Synth.Flags.Flag_Trace_Statements := True; elsif Option = "-i" then - Flag_Interractive := True; + Simul.Vhdl_Simul.Flag_Interractive := True; else return False; end if; |