synth: create abstractions for Pval (from synth-insts to synth-decls)

3 files changed, 59 insertions, 43 deletions

diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 3b0e2b2b1..7dad4d9ba 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -21,7 +21,6 @@
 with Types; use Types;
 with Mutils; use Mutils;
 
-with Netlists; use Netlists;
 with Netlists.Builders; use Netlists.Builders;
 with Netlists.Folds; use Netlists.Folds;
 with Netlists.Utils; use Netlists.Utils;
@@ -71,6 +70,53 @@ package body Synth.Decls is
       end case;
    end Create_Var_Wire;
 
+   function Type_To_Param_Type (Atype : Node) return Param_Type
+   is
+      use Vhdl.Std_Package;
+      Btype : constant Node := Get_Base_Type (Atype);
+   begin
+      if Btype = String_Type_Definition then
+         return Param_Pval_String;
+      elsif Btype = Time_Type_Definition then
+         return Param_Pval_Time_Ps;
+      else
+         case Get_Kind (Btype) is
+            when Iir_Kind_Integer_Type_Definition =>
+               return Param_Pval_Integer;
+            when Iir_Kind_Floating_Type_Definition =>
+               return Param_Pval_Real;
+            when others =>
+               return Param_Pval_Vector;
+         end case;
+      end if;
+   end Type_To_Param_Type;
+
+   function Memtyp_To_Pval (Mt : Memtyp) return Pval
+   is
+      Len    : constant Uns32 := (Mt.Typ.W + 31) / 32;
+      pragma Assert (Len > 0);
+      Vec    : Logvec_Array_Acc;
+      Off    : Uns32;
+      Has_Zx : Boolean;
+      Pv     : Pval;
+   begin
+      Vec := new Logvec_Array'(0 .. Digit_Index (Len - 1) => (0, 0));
+      Off := 0;
+      Has_Zx := False;
+      Value2logvec (Mt, 0, Mt.Typ.W, Vec.all, Off, Has_Zx);
+      pragma Assert (Off = Mt.Typ.W);
+      if Has_Zx then
+         Pv := Create_Pval4 (Mt.Typ.W);
+      else
+         Pv := Create_Pval2 (Mt.Typ.W);
+      end if;
+      for I in 0 .. Len - 1 loop
+         Write_Pval (Pv, I, Vec (Digit_Index (I)));
+      end loop;
+      Free_Logvec_Array (Vec);
+      return Pv;
+   end Memtyp_To_Pval;
+
    procedure Synth_Subtype_Indication_If_Anonymous
      (Syn_Inst : Synth_Instance_Acc; Atype : Node) is
    begin
@@ -888,10 +934,10 @@ package body Synth.Decls is
             --  simply ignored.
             null;
          when Iir_Kind_Procedure_Declaration
-           | Iir_Kind_Function_Declaration =>
+            | Iir_Kind_Function_Declaration =>
             Synth_Subprogram_Declaration (Syn_Inst, Decl);
          when Iir_Kind_Procedure_Body
-           | Iir_Kind_Function_Body =>
+            | Iir_Kind_Function_Body =>
             null;
          when Iir_Kind_Non_Object_Alias_Declaration =>
             null;
@@ -907,7 +953,7 @@ package body Synth.Decls is
             Synth_Anonymous_Type_Definition
               (Syn_Inst, Get_Type_Definition (Decl),
                Get_Subtype_Definition (Decl));
-         when  Iir_Kind_Subtype_Declaration =>
+         when Iir_Kind_Subtype_Declaration =>
             Synth_Declaration_Type (Syn_Inst, Decl);
          when Iir_Kind_Component_Declaration =>
             null;
diff --git a/src/synth/synth-decls.ads b/src/synth/synth-decls.ads
index 9aae21e2a..d0b47e3fc 100644
--- a/src/synth/synth-decls.ads
+++ b/src/synth/synth-decls.ads
@@ -20,10 +20,17 @@
 
 with Vhdl.Nodes; use Vhdl.Nodes;
 
+with Netlists; use Netlists;
 with Synth.Context; use Synth.Context;
 with Synth.Objtypes; use Synth.Objtypes;
 
 package Synth.Decls is
+   --  Return the Param_Type for ATYPE.
+   function Type_To_Param_Type (Atype : Node) return Param_Type;
+
+   --  Convert MT to a Pval.
+   function Memtyp_To_Pval (Mt : Memtyp) return Pval;
+
    --  Get the type of DECL iff it is standalone (not an already existing
    --  subtype).
    function Get_Declaration_Type (Decl : Node) return Node;
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index e0d4b62a7..01af9c63a 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -42,7 +42,6 @@ with Netlists.Concats;
 with Vhdl.Utils; use Vhdl.Utils;
 with Vhdl.Errors;
 with Vhdl.Ieee.Math_Real;
-with Vhdl.Std_Package;
 
 with Synth.Objtypes; use Synth.Objtypes;
 with Synth.Values; use Synth.Values;
@@ -385,7 +384,6 @@ package body Synth.Insts is
       Imp : Node;
       Syn_Inst : Synth_Instance_Acc;
       Inter : Node;
-      Inter_Type : Node;
       Inter_Typ : Type_Acc;
       Nbr_Inputs : Port_Nbr;
       Nbr_Outputs : Port_Nbr;
@@ -463,7 +461,6 @@ package body Synth.Insts is
 
       if Id = Id_User_Parameters then
          declare
-            use Vhdl.Std_Package;
             Descs : Param_Desc_Array (1 .. Nbr_Params);
             Ptype : Param_Type;
          begin
@@ -471,22 +468,7 @@ package body Synth.Insts is
             Nbr_Params := 0;
             while Inter /= Null_Node loop
                --  Bounds or range of the type.
-               Inter_Type := Get_Type (Inter);
-               Inter_Type := Get_Base_Type (Inter_Type);
-               if Inter_Type = String_Type_Definition then
-                  Ptype := Param_Pval_String;
-               elsif Inter_Type = Time_Type_Definition then
-                  Ptype := Param_Pval_Time_Ps;
-               else
-                  case Get_Kind (Inter_Type) is
-                     when Iir_Kind_Integer_Type_Definition =>
-                        Ptype := Param_Pval_Integer;
-                     when Iir_Kind_Floating_Type_Definition =>
-                        Ptype := Param_Pval_Real;
-                     when others =>
-                        Ptype := Param_Pval_Vector;
-                  end case;
-               end if;
+               Ptype := Type_To_Param_Type (Get_Type (Inter));
                Nbr_Params := Nbr_Params + 1;
                Descs (Nbr_Params) :=
                  (Name => Create_Inter_Name (Inter, Params.Encoding),
@@ -845,10 +827,6 @@ package body Synth.Insts is
          declare
             Inter : Node;
             Vt : Valtyp;
-            Vec : Logvec_Array_Acc;
-            Len : Uns32;
-            Off : Uns32;
-            Has_Zx : Boolean;
             Pv : Pval;
             Idx : Param_Idx;
          begin
@@ -856,22 +834,7 @@ package body Synth.Insts is
             Inter := Get_Generic_Chain (Inst_Obj.Decl);
             while Inter /= Null_Node loop
                Vt := Get_Value (Inst_Obj.Syn_Inst, Inter);
-               Len := (Vt.Typ.W + 31) / 32;
-               pragma Assert (Len > 0);
-               Vec := new Logvec_Array'(0 .. Digit_Index (Len - 1) => (0, 0));
-               Off := 0;
-               Has_Zx := False;
-               Value2logvec
-                 (Get_Memtyp (Vt), 0, Vt.Typ.W, Vec.all, Off, Has_Zx);
-               pragma Assert (Off = Vt.Typ.W);
-               if Has_Zx then
-                  Pv := Create_Pval4 (Vt.Typ.W);
-               else
-                  Pv := Create_Pval2 (Vt.Typ.W);
-               end if;
-               for I in 0 .. Len - 1 loop
-                  Write_Pval (Pv, I, Vec (Digit_Index (I)));
-               end loop;
+               Pv := Memtyp_To_Pval (Get_Memtyp (Vt));
                Set_Param_Pval (Inst, Idx, Pv);
 
                Inter := Get_Chain (Inter);