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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-06 08:36:32 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-06 08:36:32 +0200 |
| commit | b653019afa04195a2ebb7b69dd28bfe184f9fb37 (patch) | |
| tree | 9b52bd6f2a961279a3391f9cdd63109ef0aac236 /src | |
| parent | edcf4c88a67fd4a6c0b3bae30a2a6cfb1f56cc4b (diff) | |
| download | ghdl-b653019afa04195a2ebb7b69dd28bfe184f9fb37.tar.gz ghdl-b653019afa04195a2ebb7b69dd28bfe184f9fb37.tar.bz2 ghdl-b653019afa04195a2ebb7b69dd28bfe184f9fb37.zip | |
synth-vhdl_stmts: fix handling of instantiated subprograms
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 7d72d832d..f351c34f3 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -1720,7 +1720,9 @@ package body Synth.Vhdl_Stmts is Formal := Get_Formal (Assoc); pragma Assert (Formal /= Null_Node); Formal := Get_Interface_Of_Formal (Formal); - if Formal = Inter then + -- Compare by identifier, as INTER can be the generic + -- interface, while FORMAL is the instantiated one. + if Get_Identifier (Formal) = Get_Identifier (Inter) then -- Found. -- Optimize in case assocs are in order. if Assoc = Iterator.First_Named_Assoc then |