vhdl: recognize reduce operations from numeric_std.

Handle them in synthesis.

3 files changed, 86 insertions, 6 deletions

diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb
index e990aa415..26017042b 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-oper.adb
@@ -1645,17 +1645,29 @@ package body Synth.Oper is
             | Iir_Predefined_Ieee_Std_Logic_Signed_Abs_Slv =>
             return Synth_Vec_Monadic (Id_Abs);
 
-         when Iir_Predefined_Ieee_1164_And_Suv =>
+         when Iir_Predefined_Ieee_1164_And_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_And_Sgn
+            | Iir_Predefined_Ieee_Numeric_Std_And_Uns =>
             return Synth_Vec_Reduce_Monadic (Id_Red_And);
-         when Iir_Predefined_Ieee_1164_Nand_Suv =>
+         when Iir_Predefined_Ieee_1164_Nand_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn
+            | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns =>
             return Synth_Vec_Reduce_Monadic (Id_Red_And, True);
-         when Iir_Predefined_Ieee_1164_Or_Suv =>
+         when Iir_Predefined_Ieee_1164_Or_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn
+            | Iir_Predefined_Ieee_Numeric_Std_Or_Uns =>
             return Synth_Vec_Reduce_Monadic (Id_Red_Or);
-         when Iir_Predefined_Ieee_1164_Nor_Suv =>
+         when Iir_Predefined_Ieee_1164_Nor_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn
+            | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns =>
             return Synth_Vec_Reduce_Monadic (Id_Red_Or, True);
-         when Iir_Predefined_Ieee_1164_Xor_Suv =>
+         when Iir_Predefined_Ieee_1164_Xor_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn
+            | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns =>
             return Synth_Vec_Reduce_Monadic (Id_Red_Xor);
-         when Iir_Predefined_Ieee_1164_Xnor_Suv =>
+         when Iir_Predefined_Ieee_1164_Xnor_Suv
+            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn
+            | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns =>
             return Synth_Vec_Reduce_Monadic (Id_Red_Xor, True);
 
          when Iir_Predefined_Ieee_Std_Logic_Arith_Id_Uns_Uns
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index a6a0559e4..fae624d78 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -422,6 +422,48 @@ package body Vhdl.Ieee.Numeric is
       Pkg_Bit =>
         (others => Iir_Predefined_None));
 
+   Red_And_Patterns : constant Unary_Pattern_Type :=
+     (Pkg_Std =>
+        (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_And_Uns,
+         Type_Signed => Iir_Predefined_Ieee_Numeric_Std_And_Sgn),
+      Pkg_Bit =>
+        (others => Iir_Predefined_None));
+
+   Red_Nand_Patterns : constant Unary_Pattern_Type :=
+     (Pkg_Std =>
+        (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Nand_Uns,
+         Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn),
+      Pkg_Bit =>
+        (others => Iir_Predefined_None));
+
+   Red_Or_Patterns : constant Unary_Pattern_Type :=
+     (Pkg_Std =>
+        (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Or_Uns,
+         Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Or_Sgn),
+      Pkg_Bit =>
+        (others => Iir_Predefined_None));
+
+   Red_Nor_Patterns : constant Unary_Pattern_Type :=
+     (Pkg_Std =>
+        (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Nor_Uns,
+         Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn),
+      Pkg_Bit =>
+        (others => Iir_Predefined_None));
+
+   Red_Xor_Patterns : constant Unary_Pattern_Type :=
+     (Pkg_Std =>
+        (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Xor_Uns,
+         Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn),
+      Pkg_Bit =>
+        (others => Iir_Predefined_None));
+
+   Red_Xnor_Patterns : constant Unary_Pattern_Type :=
+     (Pkg_Std =>
+        (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns,
+         Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn),
+      Pkg_Bit =>
+        (others => Iir_Predefined_None));
+
    And_Patterns : constant Binary_Pattern_Type :=
      (Pkg_Std =>
         (Type_Unsigned =>
@@ -925,6 +967,18 @@ package body Vhdl.Ieee.Numeric is
                         Handle_Unary (Abs_Patterns);
                      when Name_To_Integer =>
                         Handle_To_Integer;
+                     when Name_And =>
+                        Handle_Unary (Red_And_Patterns);
+                     when Name_Nand =>
+                        Handle_Unary (Red_Nand_Patterns);
+                     when Name_Or =>
+                        Handle_Unary (Red_Or_Patterns);
+                     when Name_Nor =>
+                        Handle_Unary (Red_Nor_Patterns);
+                     when Name_Xor =>
+                        Handle_Unary (Red_Xor_Patterns);
+                     when Name_Xnor =>
+                        Handle_Unary (Red_Xnor_Patterns);
                      when others =>
                         null;
                   end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index eeaf86c72..82a45c3ed 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5793,6 +5793,20 @@ package Vhdl.Nodes is
       Iir_Predefined_Ieee_Numeric_Std_Rot_Left_Sgn_Nat,
       Iir_Predefined_Ieee_Numeric_Std_Rot_Right_Sgn_Nat,
 
+      --  Reduction
+      Iir_Predefined_Ieee_Numeric_Std_And_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_Or_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn,
+      Iir_Predefined_Ieee_Numeric_Std_And_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Nand_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Or_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Nor_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Xor_Uns,
+      Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns,
+
       --  Std_Match functions.
       Iir_Predefined_Ieee_Numeric_Std_Match_Log,
       Iir_Predefined_Ieee_Numeric_Std_Match_Uns,