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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-14 09:21:41 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-14 09:21:41 +0100 |
| commit | c4baaa1a0419517aad50e43893c8400af4e2b7a0 (patch) | |
| tree | 0e7c2db324d2651aad52dab010b24a184a7545bc /src | |
| parent | 2386da54bc6ac259f88e6d9cbe98c29114aba47c (diff) | |
| download | ghdl-c4baaa1a0419517aad50e43893c8400af4e2b7a0.tar.gz ghdl-c4baaa1a0419517aad50e43893c8400af4e2b7a0.tar.bz2 ghdl-c4baaa1a0419517aad50e43893c8400af4e2b7a0.zip | |
vhdl-ieee-std_logic_arith: fix warnings.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index 352205585..a4183d9b4 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -104,8 +104,7 @@ package body Vhdl.Ieee.Std_Logic_Arith is Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Int_Slv, Type_Log => - Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv, - others => Iir_Predefined_None), + Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Log_Slv), Type_Signed => (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv, @@ -114,8 +113,7 @@ package body Vhdl.Ieee.Std_Logic_Arith is Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv, Type_Log => - Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv, - others => Iir_Predefined_None), + Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv), Type_Int => (Type_Unsigned => Iir_Predefined_Ieee_Std_Logic_Arith_Add_Int_Uns_Slv, @@ -127,9 +125,7 @@ package body Vhdl.Ieee.Std_Logic_Arith is Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Uns_Slv, Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv, - others => Iir_Predefined_None), - others => - (others => Iir_Predefined_None)), + others => Iir_Predefined_None)), Type_Signed => (Type_Signed => (Type_Signed => @@ -139,8 +135,7 @@ package body Vhdl.Ieee.Std_Logic_Arith is Type_Int => Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn, Type_Log => - Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn, - others => Iir_Predefined_None), + Iir_Predefined_Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn), Type_Unsigned => (Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn, @@ -152,9 +147,7 @@ package body Vhdl.Ieee.Std_Logic_Arith is Type_Log => (Type_Signed => Iir_Predefined_Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn, - others => Iir_Predefined_None), - others => - (others => Iir_Predefined_None)), + others => Iir_Predefined_None)), Type_Unsigned => (Type_Unsigned => (Type_Unsigned => |